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DAC1408D650
Dual 14-bit DAC; up to 650 Msps; 2x, 4x or 8x interpolating
Rev. 02 -- 11 August 2010 Preliminary data sheet
1. General description
The DAC1408D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2x, 4x or 8x interpolating filters optimized for multi-carrier WCDMA transmitters. Because of its digital on-chip modulation, the DAC1408D650 allows the complex pattern provided through lane 0, lane 1, lane 2 and lane 3, to be converted from baseband to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register. The DAC1408D650 also includes a 2x, 4x or 8x clock multiplier which provides the appropriate internal clocks and an internal regulation to adjust the output full scale current. The input data format is serial according to JESD204A specification. This new interface has numerous advantages over the traditional parallel one: easy PCB layout, lower radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum number of lanes of the DAC1408D650 is 4 and its maximum serial data rate is 3.125 Gbps. The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output clock period between several DAC devices. MDS incorporates modes: Master/slave and All slave mode. It guarantees a maximum skew of one output clock period between two devices.
2. Features and benefits
Dual 14-bit resolution 650 Msps maximum update rate Selectable 2x, 4x or 8x interpolation filters Input data rate up to 312.5 Msps Very low noise cap free integrated PLL 32-bit programmable NCO frequency Four JESD204A serial input lanes 1.8 V and 3.3 V power supplies LVDS compatible clock inputs IMD3: 76 dBc; fs = 640 Msps; fo = 140 MHz ACPR: 71 dBc; two carriers WCDMA; fs = 640 Msps; fo = 133 MHz Typical 1.24 W power dissipation at 4x interpolation, PLL off and 640 Msps Power-down mode and Sleep modes Differential scalable output current from 1.6 mA to 22 mA On-chip 1.25 V reference External analog offset control (10-bit auxiliary DACs) Internal digital offset control Inverse (sin x) / x function
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A Fully compatible SPI port Industrial temperature range from -40 C to +85 C Integrated PLL can be bypassed Embedded complex modulator
Two's complement or binary offset data format LMF = 421 or LMF = 211 support Differential CML receiver with embedded termination Synchronization of multiple DAC devices outputs
3. Applications
Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication: LMDS/MMDS, point to point Direct Digital Synthesis (DDS) Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment (ATE)
4. Ordering information
Table 1. Ordering information Package Name DAC1408D650HN/C1 HVQFN64 Description Version plastic thermal enhanced very thin quad flat package; no leads; SOT804-3 64 terminals; body 9 x 9 x 0.85 mm; exposed die pad Type number
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
2 of 98
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5. Block diagram
SDO SDIO CSB SCLK
INTER LANE ALIGNMENT
VIN_P1 L1 VIN_N1
LANE PROC
FRAME ASSEMBLY
Preliminary data sheet Rev. 02 -- 11 August 2010 3 of 98
DAC1408D650 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
NXP Semiconductors
SPI CONTROL REGISTERS
NCO 32 bits frequency setting 16 bits phase adjustment cos sin
10 BITS OFFSET CONTROL
AUX. DAC
AUXAP AUXAN
SYNC_OUTP SYNC_OUTN
DIGITAL LAYER PROCESSING JESD204A LANE PROC
10 BITS GAIN CONTROL FIR 1 FIR 2 FIR 3 X Sin X I DAC IOUTAN IOUTAP +
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
VIN_P0 L0 VIN_N0
x2
x2
x2
DAC1408D
VIN_P2 L2 VIN_N2
SINGLE SIDE BAND MODULATOR FIR 3 X Sin X
OFFSET CONTROL
REF. BANDGAP AND BIASING
DACFSADJ GAPOUT
LANE PROC
FIR 1
FIR 2
VIN_P3 L3 VIN_N3
+
LANE PROC
Q DAC
IOUTBP IOUTBN
x2
x2
x2
10 BITS GAIN CONTROL CLOCK GENERATOR UNIT MULTI-DAC SYNCHRONISATION 10 BITS OFFSET CONTROL AUX. DAC AUXBP AUXBN
DAC1408D650
CLK_INP
CLK_INN
RESET_N
MDS_OUTP
MDS_OUTN
001aal068
Fig 1.
Block diagram
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
6. Pinning information
6.1 Pinning
50 SYNC_OUTN 51 SYNC_OUTP
59 VDDD(1v8)
54 VDDD(1v8)
terminal 1 index area SDO SDIO SCLK VDDD(1v8) SCS_N RESET_N n.c. VIRES GAPOUT 1 2 3 4 5 6 7 8 9
49 VDDD(1v8) 48 n.c. 47 VDDD(1v8) 46 MDS_N 45 MDS_P 44 VDDA(1v8) 43 AGND 42 CLKINN 41 CLKINP 40 AGND 39 VDDA(1v8) 38 VDDA(1v8) 37 AGND 36 AUXAN 35 AUXAP 34 VDDA(3v3) 33 AGND VDDA(1v8) 32
005aaa150
61 VIN_N3
57 VIN_N2
DAC1408D HVQFN64
VDDA(1v8) 10 VDDA(1v8) 11 AGND 12 AUXBN 13 AUXBP 14 VDDA(3v3) 15 AGND 16 VDDA(1v8) 17 AGND 18 VDDA(1v8) 19 VDDA(1v8) 20 AGND 21 IOUTBN 22 IOUTBP 23 AGND 24 AGND 25 IOUTAP 26 IOUTAN 27 AGND 28 VDDA(1v8) 29 VDDA(1v8) 30 AGND 31
Transparent top view
Fig 2.
Pin configuration
6.2 Pin description
Table 2. Symbol SDO SDIO SCLK VDDD(1V8) SCS_N RESET_N n.c. VIRES GAPOUT VDDA(1V8) VDDA(1V8)
DAC1408D650
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 Type[1] O I/O I P I I I/O I/O P P Description SPI data output SPI data input/output SPI clock digital supply voltage 1.8 V SPI chip select (active LOW) general reset (active LOW) not connected DAC biasing resistor bandgap input/output voltage analog supply voltage 1.8 V analog supply voltage 1.8 V
(c) NXP B.V. 2010. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Preliminary data sheet
Rev. 02 -- 11 August 2010
52 VIN_N0
60 VIN_P3
58 VIN_P2
55 VIN_P1
53 VIN_P0
56 VIN-N1
64 JTAG
63 n.c.
62 n.c.
4 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Pin description ...continued Pin 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Type[1] G O O P G P G P P G O O G G O O G P P G P G P O O G P P G I I G P I/O I/O P P O O Description analog ground complementary auxiliary DAC B output auxiliary DAC B output analog supply voltage 3.3 V analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog supply voltage 1.8 V analog ground complementary DAC B output current DAC B output current analog ground analog ground DAC A output current complementary DAC A output current analog ground analog supply voltage 1.8 V analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground analog supply voltage 3.3 V auxiliary DAC A output current complementary auxiliary DAC A output current analog ground analog supply voltage 1.8 V analog supply voltage 1.8 V analog ground clock input complementary clock input analog ground analog supply voltage 1.8 V multi-devices synchronization complementary multi-devices synchronization digital supply voltage 1.8 V not connected digital supply voltage 1.8 V synchronization request to transmitter, complementary output synchronization request to transmitter
(c) NXP B.V. 2010. All rights reserved.
Table 2. Symbol AGND AUXBN AUXBP VDDA(3V3) AGND VDDA(1V8) AGND VDDA(1V8) VDDA(1V8) AGND IOUTBN IOUTBP AGND AGND IOUTAP IOUTAN AGND VDDA(1V8) VDDA(1V8) AGND VDDA(1V8) AGND VDDA(3V3) AUXAP AUXAN AGND VDDA(1V8) VDDA(1V8) AGND CLKINP CLKINN AGND VDDA(1V8) MDS_P MDS_N VDDD(1V8) n.c. VDDD(1V8)
SYNC_OUTN SYNC_OUTP
DAC1408D650
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Preliminary data sheet
Rev. 02 -- 11 August 2010
5 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Pin description ...continued Pin 52 53 54 55 56 57 58 59 60 61 62 63 64 H[2] Type[1] I I P I I I I P I I I G Description serial interface lane 0 negative input serial interface lane 0 positive input digital supply voltage 1.8 V serial interface lane 1 positive input serial interface lane 1 negative input serial interface lane 2 negative input serial interface lane 2 positive input digital supply voltage 1.8 V serial interface lane 3 positive input serial interface lane 3 negative input not connected not connected JTAG test mode select (must be grounded) ground
Table 2. Symbol VIN_N0 VIN_P0 VDDD(1V8) VIN_P1 VIN_N1 VIN_N2 VIN_P2 VDDD(1V8) VIN_P3 VIN_N3 n.c. n.c. JTAG GND
[1] [2]
P: power supply; G: ground; I: input; O: output. H = heatsink (exposed die pad to be soldered to GND. A minimum of 81 thermal vias are required)
7. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDA(3V3) VDDA(1V8) VDDD Tstg Tamb Tj
[1] [2]
Parameter analog supply voltage (3.3 V) analog supply voltage (1.8 V) digital supply voltage storage temperature ambient temperature junction temperature
Conditions
[1] [2] [2]
Min -0.5 -0.5 -0.5 -55 -40 -40
Max +4.6 +2.5 +2.5 +150 +85 +125
Unit V V V C C C
The supply voltage VDDA(3V3) may have any value between -0.5 V and +4.6 V provided that the supply voltage differences VCC are respected. The supply voltages VDDA(1V8) and VDDD may have any value between -0.5 V and +2.5 V provided that the supply voltage differences VCC are respected.
8. Thermal characteristics
Table 4. Symbol Rth(j-a) Rth(j-c)
[1]
Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions
[1] [1]
Typ 18.7
Unit K/W K/W
In compliance with JEDEC test board, in free air.
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
9. Characteristics
Table 5. Characteristics VDDA(1V8) = VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND and GND are shorted together; Tamb = -40 C to +85 C; typical values measured at VDDA(1V8) = VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; PLL off unless otherwise specified. Symbol VDDA(3V3) VDDD(1V8) VDDA(1V8) IDDA(3V3) IDDD(1V8) IDDA(1V8) IDDD Ptot Parameter analog supply voltage (3.3 V) digital supply voltage (1.8 V analog supply voltage (1.8 V) analog supply current (3.3 V) digital supply current, (1.8 V) analog supply current, (1.8 V) digital supply current difference fo = 19 MHz; fs = 640 Msps; 4x interpolation; NCO on fo = 19 MHz; fs = 640 Msps; 4x interpolation; NCO on fo = 19 MHz; fs = 640 Msps; 4x interpolation; NCO on X/sin X function on; fs = 640 Msps Conditions Test[1] I I I I I I I C Min 3.0 1.7 1.7 Typ 3.3 1.8 1.8 43 352 408 53 0.8 Max 3.6 1.9 1.9 Unit V V V mA mA mA mA W
total power dissipation fs = 640 Msps; 4x interpolation; NCO off; DAC Q off fs = 640 Msps; 4x interpolation; NCO off fs = 640 Msps; 4x interpolation; NCO on fs = 625 Msps; 2x interpolation; NCO off fs = 625 Msps; 2x interpolation; NCO on Complete device; Power-down mode DAC A and DAC B; Power-down mode DAC A and DAC B; Sleep mode
C C C C
-
1.24 1.5 1.36 1.54
-
W W W W
Power-down mode; fo = 19 MHz; fs = 640 Msps; 4x interpolation; NCO on I I I 0.05 0.6 0.92 W W W
Clock inputs (CLKINN, CLKINP)[2] Vi Vidth Ri Ci VIL
DAC1408D650
input voltage input differential threshold voltage input resistance input capacitance LOW-level input voltage
range: CLK+ or CLK- |Vgpd| < 50 mV[3] |Vgpd| < 50 mV[3]
C C D D C
825 -100 GND
10 0.5 -
1575 +100 0.54
mV mV M pF V
Digital inputs (SDIO, SCLK, SCS_N, RESET_N)
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Preliminary data sheet
Rev. 02 -- 11 August 2010
7 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 5. Characteristics ...continued VDDA(1V8) = VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND and GND are shorted together; Tamb = -40 C to +85 C; typical values measured at VDDA(1V8) = VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; PLL off unless otherwise specified. Symbol VIH IIL IIH Parameter HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level output voltage HIGH-level output voltage common-mode input voltage peak-to-peak differential input voltage Vtt source impedance differential input impedance common-mode output voltage peak-to-peak differential output voltage peak-to-peak differential output voltage output load capacitance input capacitance between pins GND and MDS_N or MDS_P between pins GND and MDS_N or MDS_P register value = 00h register = default value compliance range D D D C C VIL = 0.54 V VIH = 1.26 V Conditions Test[1] C I I Min 1.26 Typ 1 1 Max VDDD Unit V A A
Digital outputs (SDO, SDIO) VOL VOH C C V V
Digital inputs (Vin_p/Vin_n)[4] VI(cm) VI(dif)(p-p) D D 0.68 175 0.78 1.40 1000 V mV
Ztt Zi
D D
-
0.7 100
-

Digital outputs (SYNC_OUTN/SYNC_OUTP)[5] Vo(cm) Vo(dif)(p-p) C C 0.79 0.12 0.98 0.48 1.46 0.96 V V
Digital inputs/outputs (MDS_N/MDS_P) Vo(dif)(p-p) D 600 mV
Co(L) Ci
D D
-
0.3
10 -
pF pF
Analog outputs (IOUTAP, IOUTAN, IOUTBP, IOUTBN) IO(fs) VO Ro Co EO EG full-scale output current output voltage output resistance output capacitance offset error variation gain error variation D 1.8 1.6 20 250 3 6 18 mA mA k pF ppm/C ppm/C
VDDA(3V3) V
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 5. Characteristics ...continued VDDA(1V8) = VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND and GND are shorted together; Tamb = -40 C to +85 C; typical values measured at VDDA(1V8) = VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; PLL off unless otherwise specified. Symbol VO(ref) IO(ref) VO(ref) Parameter reference output voltage reference output current reference output voltage variation auxiliary output current differential outputs auxiliary output voltage auxiliary DAC monotonicity data rate compliance range guaranteed external voltage 1.2 V Conditions Test[1] C C C Min Typ 1.25 40 117 Max Unit V A ppm/C Reference voltage output (GAPOUT)
Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN) IO(aux) VO(aux) NDAC(aux)mono I D D 0 2.2 10 2 mA V bits
Input timing (Vin_p / Vin_n) fdata 2x interpolation 4x interpolation 8x interpolation fbit fs ts fNCO fstep fNCO fstep SFDR bit rate sampling rate settling time NCO frequency step frequency NCO frequency step frequency reg value = 00000000h reg value = F8000000h Dynamic performances spurious-free dynamic fdata = 80 Msps; fs = 640 Msps; x8; BW = fdata / 2; PLL on range C 76 fo = 4 MHz at -1 dBFS fdata = 160 Msps; fs = 640 Msps; x4; BW = fdata / 2 fo = 19 MHz at -1 dBFS fo = 19 MHz at -1 dBFS C I 74 74 dBc dBc fdata = 312.5 Msps; fs = 625 Msps; x2; BW = fdata / 2 dBc up to 0.5 LSB register value = 00000000h register value = FFFFFFFFh Low power NCO frequency range; fs = 650 Msps D D D 0 630 20.3 MHz MHz MHz serial input Output timing (IOUTAP, IOUTAN, IOUTBP, IOUTBN) D D D D D 20 0 650 0.151 650 Msps ns MHz MHz Hz D D D D 0.5 312.5 162.5 81.25 3.125 Msps Msps Msps Gbps
NCO frequency range; fs = 650 Msps
DAC1408D650
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Preliminary data sheet
Rev. 02 -- 11 August 2010
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 5. Characteristics ...continued VDDA(1V8) = VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND and GND are shorted together; Tamb = -40 C to +85 C; typical values measured at VDDA(1V8) = VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; PLL off unless otherwise specified. Symbol SFDRRBW Parameter Conditions Test[1] I Min Typ 80 Max Unit dBc restricted bandwidth fs = 640 Msps; spurious-free dynamic 4x interpolation; range fo = 133 MHz at -1 dBFS; BW = 100 MHz fs = 640 Msps; 4x interpolation; fo = 133 MHz at -1 dBFS; BW = 20 Mhz IMD3 third-order intermodulation distortion fo1 = 95 MHz; fo2 = 97 MHz; fs = 640 Msps; 4x interpolation fo1 = 153.1 MHz; fo2 = 154.1 MHz; fs = 640 Msps; 4x interpolation fo1 = 137 MHz; fo2 = 143 MHz; fs = 640 Msps; 4x interpolation ACPR adjacent channel power ratio 1 carrier; BW = 5 MHz 2 carriers; BW = 10 MHz 4 carriers; BW = 20 MHz 1 carrier; BW = 5 MHz 2 carriers; BW = 10 MHz 4 carriers; BW = 20 MHz NSD noise spectral density fs = 640 Msps; 4x interpolation; fo = 133 MHz at 0 dBFS
C
-
84
-
dBc
C
[6]
-
79
dBc
I
[6]
-
76
-
dBc
C
[6]
-
76
-
dBc
NCO on; 4x interpolation; fs = 640 Msps; fo = 96 MHz C C C C C C I 72 72 69 71 71 68 -155 dB dB dB dB dB dB dBc/Hz
NCO on; 4x interpolation; fs = 640 Msps; fo = 133MHz
[1] [2] [3] [4] [5] [6]
D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. CLKINP/CLKINN inputs are at differential LVDS levels. An external termination resistor with a value of between 80 and 120 (see Figure 16) should be connected across the pins. |Vgpd| represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance and the inductance between the receiver and the driver circuit ground voltage. Vin_p and Vin_n inputs are differential CML inputs. There are terminated internally to Vtt via 50 (see Figure 4). SYNC_OUTP/SYNC_OUTN outputs are differential LVDS outputs. They must be terminated by a resistor with a value of between 80 and 120 . IMD3 rejection with -6 dBFs/tone.
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10. Application information
10.1 General description
The DAC1408D650 is a dual 14-bit DAC operating up to 650 Msps. With a maximum input data rate of up to 312.5 Msps and a maximum output sampling rate of 650 Msps, the DAC1408D650 allows more flexibility for wide bandwidth and multi-carrier systems. Combined with its quadrature modulator and its 32-bit NCO, the DAC1408D650 simplifies the frequency selection of the system. This is also possible because of the 2x, 4x or 8x interpolation filters that remove undesired images. DAC1408D650 supports the following JESD204A key features:
* 8-bit/10-bit decoding * Code group synchronization * interlane alignment * * * *
1+x
14
+x
15
scrambling polynomial
Character replacement TX/RX synchronization management via SYNC signals Multiple Converter Device Alignment-Multiple Lanes (MCDA-ML) device
DAC1408D650 can be interfaced with any logic device that features high speed SERDES functionality. This macro is now widely available in FPGA from different vendors. Standalone SERDES ICs can also be used. To enhance the intrinsic board layout simplification of the JESD204A standard, NXP includes polarity swapping for each of the lanes and additionally offers lane swapping. Each physical lane can be configured as being logically lane0, lane1, lane2 or lane3. This device is MCDA-ML compliant, offering interlane alignment between several devices. Samples alignment between devices is maintained up to output level because of an NXP proprietary mechanism. One device is configured as the master and all the others are configured as slaves. These will automatically align their output samples to the master ones. Therefore, a system with several DAC1408D650 can produce data with a guaranteed alignment of less than 1 DAC output clock period. Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN. This provides a full-scale output current of up to 20 mA. An internal reference is available for the reference current which is externally adjustable using pin VIRES. The DAC1408D650 must be configured before operating. Therefore, it features an SPI slave interface to access internal registers. Some of these registers also provide information about the JESD204A interface status. The DAC1408D650 requires both 3.3 V and 1.8 V. 1.8 V has separate digital and analog power supply pins. The clock input is LVDS compliant.
DAC1408D650
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
11 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.2 JESD204A receiver
internal configuration interface ILA (Inter-lane Alignment)
8b
SYNC_OUT
10b
RX CONTROLLER
lane#
DES
CLOCK ALIGN
10b
10b
K-DETECT 8b 10b/8b
FA (Frame Assembly)
SYNC AND WORD ALIGN
8b 8b 8b 8b
DESCRAMBLER
14b
14b
frame clock
001aak161
The descrambler can be enabled/disabled
Fig 3.
JESD204A receiver
The JEDEC204A defines the following parameters: L is the number of lanes per link M is the number of converters per device F is the number of bytes per frame clock period The DAC1408D650 supports both LMF = 421 and LMF = 211. The current setting is configurable via the SPI registers interface. The complete Digital Layer Processing (DLP) adds a variable delay on each lane path. This is mainly because of the interlane alignment.
Table 6. td
[1] [2]
Digital Layer Processing Latency Conditions digital layer processing delay Test[1] D Min 13 Typ Max 28 Unit Cycle[2] delay time
Symbol Parameter
D = guaranteed by design. Frame clock cycle.
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.2.1 Lane input
Each lane is CML compliant. It is terminated to a common voltage with an integrated 50 resistor.
Vin_p
50
50
Vin_n
Ztt
Vtt
001aak166
Fig 4.
Lane input termination
The common mode voltage is programmable. See Table 76 on page 55 for the register value. DC coupling is only possible if both the DAC and the transmitter have the same common-mode voltage. If this is not the case AC coupling is required.
VDD1
VDD2
50
50
50
50
50
50
50
50
Zdiff = 100
Zdiff = 100
data in + data in -
data in + data in -
001aak162
001aak163
Fig 5.
DC coupling
Fig 6.
AC coupling
The deserializer performs the incoming data clock recovery and also the serial to parallel conversion. Therefore, each lane includes its own PLL that must first lock. Then the clock alignment module transfers the data from the regenerated clock to the frame clock domain. The frequency of both clocks is the same but the phase relation between the clocks is unknown.
10.2.2 Sync and word align
As stated in JESD204A, the transmitter and the receiver first have to synchronize. This is achieved through SYNC_OUT signals and a SYNC pattern (K28.5 symbol). The receiver (i.e. DAC1408D650) first drives its SYNC outputs. The SYNC signal/pattern is continuously sent until the receiver deasserts the SYNC signal.
DAC1408D650 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
The lane processing makes use of the SYNC-patterns to synchronize the datastream, determine the initial running disparity and extract the 10-bit word from the incoming datastream (word-alignment). The SYNC signal is also used during normal operation by the DAC1408D650 to request a link re-initialization. This occurs when the 8b/10b module loses synchronization. The SYNC_OUT signal conforms to LVDS signaling. Its common mode voltage and its differential peak-to-peak amplitude (see Table 78) can be programmed using registers. SYNC_OUT is synchronous with the frame clock.
tFS_R(max) tFS_R(min)
SYNC_OUT
CLK
001aak165
Fig 7. Table 7. td
[1]
SYNC_OUT timing SYNC_OUT timing Conditions frame clock to sync Test[1] C Min Typ Max Unit ns delay time
Symbol Parameter
C = guaranteed by characterization.
10.2.3 Comma detection and word align
This stage monitors the datastream for code characters (comma detection), decodes the words to bytes (octets) and performs optional character replacement as part of frame/lane alignment monitoring and correction. This module provides the required control signals to the RX-controller and ILA. This module decodes the 10-bit words into 8-bit words (octets). The decoding table is specified in the IEEE Std.802.3-2005 specification. During decoding, the disparity is calculated according to the disparity rules mentioned in the same specification IEEE Std.802.3-2005. When the disparity counter is more than +2 or less than -2, an error will be generated. The following comma symbols are detected during data transmission irrespective of the running disparity: /K/=K28.5 /F/=K28.7 /A/=K28.3 /R/=K28.0 /Q/=K28.4
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A flag is sent to the control interface to reflect detected commas in registers. The following flags are also triggered according to the following definitions:
* VALID: a code group that is found in the column of the 8b/10b decoding tables
according to the current running disparity.
* DISPARITY ERROR: The received code group exists in the 8b/10b decoding table,
but is not found in the proper column according to the current running disparity.
* NOT-IN-TABLE ERROR: The received code group is not found in the 8b/10b
decoding table for either disparity.
* INVALID: a code group that either shows a disparity error or that does not exist in the
8b/10b decoding table. DAC1408D650 supports character replacement whatever the state of the descrambler. When scrambling is not active, the received K28.3 /A/ or K28.7 /F/ will be replaced by the previous sample. When scrambling is active, the corresponding data octet D28.3 (0xC) or D28.7 (0xFC) will be used.
10.2.4 Descrambler
The used descrambler is the 16-bit parallel self-synchronous descrambler based on the polynomial 1 + x
14
+ x . This processing can be turned off.
15
10.2.5 Interlane alignment
This feature removes strict PCB design skew compensation between the lanes. 10.2.5.1 Single device operation This module handles the alignment of the four data streams. Because of interlane skew and each PLL per lane concept, these alignment characters may be received at different times by the receivers. After the synchronization period, the lock signal will be high. This enables the receiving of K28.3 /A/ characters. The /A/-characters provided in the initial alignment sequence are then used to align the four data streams. With the bit field sel_ila (two bits) (refer to Table 87 "ILA_CNTRL register (address 07h) bit description"), one can select the used K28.3 /A/ symbol ("00" use the 1st /A/ symbol, "01" use the 2nd /A/ symbol, "10" use the 3rd /A/ symbol, "11" use the 4th /A/ symbol) during the initial lane alignment. When all receivers have received their first selected /A/, they start propagating the received data to the frame assembly module at the same point in time. This module can compensate up to +7/-7 frame clock period misalignment between the lanes. When initial lane alignment is not supported, the manual alignment mode can be used. After the initial ILA sequence, the lane alignment monitoring starts. When a K28.3 /A/ symbol is received among the user data:
* its position is compared to the value of the alignment monitor counter * if two successive K28.3 /A/ symbols have been received at a wrong position, a
realignment takes place
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* if the buffers are empty or overflow, this will be indicated by the registers buff_err_ln0
to buff_err_ln3 10.2.5.2 Multi-device operation DAC1408D650 implements a multi-device interlane alignment that guarantees a skew of less than one output period between them. Two modes are available: Master/slave and All slave. Both make use of the MDS_P and MDS_N pins.
mds_A_out ref_A MDS_A COMP mds_A
I LANES DIG BUFFER Q
SYNC~
CLK MGMT DAC CK
001aal073
Fig 8.
Multi-Device Synchronization (MDS) implementation
Each DAC device of the system generates its own reference (ref_A on Figure 8). If configured as slave, an early-late comparator compares the internal reference with the external reference provided by the MDS pins. The comparator controls an internal buffer that is used to delay the samples.
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10.2.5.3
Master/slave mode The external reference is provided by one of the DACs (the master DAC), which has to be configured to be able to do this. The others are set to Slave mode.
mds_out ref_A COMP mds_in
I DIG BUFFER Q MASTER DAC 0
CLK MGMT SYNC_0 DAC_0
mds_out ref_A COMP mds_in
I DIG BUFFER Q SLAVE DAC 1
TX SYNC_1
CLK MGMT DAC_1
mds_out ref_A COMP mds_in
I DIG BUFFER Q SLAVE DAC 2
CLK MGMT SYNC_2 DAC_2
CLOCK DISTRIBUTION
REF_CLOCK
001aal070
Fig 9.
DAC1408D650
Master-slave mode
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The MDS signal generated by the master DAC must reach all slaves within one DAC output clock period. This induces PCB layout constraints for the MDS signal and also for the clock distribution. Because trace lengths differ, the clock edges will reach each of the DACs at different times.
TDAC
ref clock
PH01 master clock
PH02 slave 1 clock
PH03 slave 2 clock
001aal072
Fig 10. Clock skew case 1: Master is farthest
The worst case clock skew is given by t 1 = PH01 - PH03 , where PH0x represents the trace delay and also the clock skew at the output of the clock generator. The maximum allowable trace delay for the MDS signal is given by t = TDAC - t 1 .
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TDAC
ref clock
PH01 master clock
PH02 slave 1 clock
PH03 slave 2 clock
001aal071
Fig 11. Clock skew case 2: Master is closest
The worst case clock skew is given by t 2 = PH03 - PH01 . The minimum allowable trace delay for the MDS signal is given by t = t 2 . In real applications, the master DAC can be anywhere and both conditions must be satisfied: t 2 < t mds < TDAC - t 1 . Example:
* * * *
clock generator skew = 80 ps FR4 substrate 15 cm/ns delay clock trace length difference = 3 cm and 4 cm Output sampling rate = 650 Msps
200 ps + 80 ps < tmds < 1538 ps - (266 ps + 80 ps) 280 ps < tmds < 1192 ps 4.2 cm < Lmds < 17.8 cm
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10.2.5.4
All slave mode The external reference is provided by the JESD204A transmitter. All DACs are configured in Slave mode.
mds_out ref_A Jesd204A TX COMP mds_in
I DIG BUFFER Q SLAVE DAC 0
CLK MGMT SYNC_0 DAC_0
mds_out ref_A COMP mds_in
I DIG BUFFER Q SLAVE DAC 1
/A/ INSERTION SYNC_1
CLK MGMT DAC_1
mds_out ref_A COMP mds_in
I DIG BUFFER Q SLAVE DAC 2
CLK MGMT SYNC_2 dT MDS DAC_2
CLOCK DISTRIBUTION
REF_CLOCK
001aal069
Fig 12. All slave mode
The MDS signal is now driven from the transmitter. It is generated at the end of the interlane alignment phase (see the JESD204A standard for details). The transmitter must also compensate for the DAC latency. Although the DAC has an internal samples delay line, it cannot handle large delays. In this mode, PCB layout is also important. The following delay equation applies: t < t mds < TDAC - t , where t is the clock skew considered close to DAC pins.
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10.2.6 Frame assembly
DAC1408D650 supports only /F/ = 1, which means that every frame clock period carries one byte per lane. Frame assembly combines the octet of lane_0 with the six MSB bits of lane_1 and reassemble the original 14-bit sample. The same is done for lane_2 and lane_3. Tail bits are dropped. The frame assembler also handles error previously triggered. If scrambling is enabled: If a nit_err (not in table error) or kout_unexp (unexpected control character) occurs in lane_0 and/or lane_1, the previous 14-bit sample is repeated twice for I (lane_0, lane_1). The same is done for Q (lane_2, lane_3). If scrambling is disabled: if a nit_err (not in table error) or kout_unexp (unexpected control character) occurs in lane_0 and/or lane_1, the previous 14-bit sample will be repeated once for I (lane_0, lane_1). The same is done for Q (lane_2, lane_3).
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SERIAL CLOCK 3.125 GHz encoded octet /10 b9 b8 b7 DESERIALIZER b6
CHARACTER CLOCK 312.5 MHz
FRAME CLOCK 312.5 MHz /F
scrambled octet S7 S6 S5 10b/8b S4 S3 S2 S1 S0 lane 0
ON/OFF
byte 0 D13 D12 D11 D10 D09 D08 D07 D06 D13 D12
b5 b4 b3 b2 b1 b0 encoded octet
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
DESCRAMBLER
D11 scrambled octet S7 DESCRAMBLER S6 S5 10b/8b S4 S3 S2 S1 S0 lane 1 F = 1 byte scrambled octet S7 DESCRAMBLER S6 S5 10b/8b S4 S3 S2 S1 S0 lane 2 ON/OFF byte 2 D13 D12 D11 D10 D09 D08 D07 D06 ON/OFF byte 1 D05 D04 D03 D02 D01 D00 T FRAME ASSEMBLY T D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 M = 2 converters D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 DAC1 DAC0
/10
b9 b8 b7
DESERIALIZER
b6 b5 b4 b3 b2 b1 b0 encoded octet
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
/10
b9 b8 b7
DESERIALIZER
b6 b5 b4 b3 b2 b1 b0 encoded octet
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
D01 scrambled octet S7 DESCRAMBLER S6 S5 10b/8b S4 S3 S2 S1 S0 lane 3 ON/OFF byte 3 D05 D04 D03 D02 D01 D00 T T
001aak164
/10
b9 b8 b7
D00
DESERIALIZER
b6 b5 b4 b3 b2 b1 b0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Fig 13. Frame assembly
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10.3 Serial Peripheral Interface (SPI)
10.3.1 Protocol description
The DAC1408D650 serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that define the operating modes of the chip in both Write mode and Read mode. This interface can be configured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire type (SDIO and SDO as unidirectional pin, input and output port respectively). In both configurations, SCLK acts as the serial clock and SCS_N acts as the serial chip select bar. Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW assertion to drive the chip with two bytes to five bytes, depending on the content of the instruction byte (see Table 9).
RESET_N
SCS_N
SCLK
SDIO SDO (optional)
R/W
N1
N0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
001aaj812
R/W indicates the mode access, (see Table 8):
Fig 14. SPI protocol Table 8. R/W 0 1 Read or Write mode access description Description Write mode operation Read mode operation
In Table 9 below, N1 and N0 indicate the number of bytes transferred after the instruction byte.
Table 9. N1 0 0 1 1 Number of bytes to be transferred N0 0 1 0 1 Number of bytes transferred 1 2 3 4
A[4:0] indicates which register is being addressed. In case of a multiple transfer, this address points to the first register accessed and is internally decreased after each following data phase.
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10.3.2 SPI timing description
The SPI interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in Figure 15.
tw(RESET_N) RESET_N 50 % tsu(SCS_N) SCS_N 50 % tw(SCLK) SCLK 50 % th(SCS_N)
SDIO
50 % th(SDIO) tsu(SDIO)
001aaj813
Fig 15. SPI timing diagram
The SPI timing characteristics are given in Table 10.
Table 10. Symbol fSCLK tw(SCLK) tsu(SCS_N) th(SCS_N) tsu(SDIO) th(SDIO) tw(RESET_N) SPI timing characteristics Parameter SCLK frequency SCLK pulse width SCS_N set-up time SCS_N hold time SDIO set-up time SDIO hold time RESET_N pulse width Min 30 20 20 10 5 30 Typ Max 15 Unit MHz ns ns ns ns ns ns
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10.4 Clock input
The DAC1408D650 has one differential clock input, CLKINN/CLKINP.
Z = 50
CLKP
LVDS
Zdiff = 100
LVDS
Z = 50
CLKN
001aah021
Fig 16. LVDS clock configuration
VDDA(1V8)
1.1 k Z = 50 100 nF
CLKP
55
CML
Zdiff = 100 55 100 nF
LVDS
Z = 50
CLKN
2.2 k
100 nF
AGND
001aah020
Fig 17. Interfacing CML to LVDS
The DAC1408D650 can operate with a clock frequency up to 312.5 MHz or up to 650 MHz if the internal PLL is bypassed. The clock input can be LVDS (see Figure 16) but it can also be interfaced with CML (see Figure 17). During the reset phase (RESET_N asserted), the clock must be stable and running. This ensures a proper reset of the complete device. The device has no embedded power-on-reset feature. Driving the RESET_N pin to set the device to its default state is mandatory.
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10.5 FIR filters
The three interpolation FIR filters have a stop band attenuation of at least 80 dBc and a pass band ripple of less than 0,0005 dB.
Table 11. Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(23) H(24) H(25) H(26) H(27) H(28) Interpolation filter coefficients Second interpolation filter Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) Upper H(23) H(22) H(21) H(20) H(19) H(18) H(17) H(16) H(15) H(14) H(13) Value -2 0 17 0 -75 0 238 0 -660 0 2530 4096 Third interpolation filter Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) Upper H(15) H(14) H(13) H(12) H(11) H(10) H(9) Value -39 0 273 0 -1102 0 4964 8192 Upper H(55) H(54) H(53) H(52) H(51) H(50) H(49) H(48) H(47) H(46) H(45) H(44) H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) Value -4 0 13 0 -34 0 72 0 -138 0 245 0 -408 0 650 0 -1003 0 1521 0 -2315 0 3671 0 -6642 0 20756 32768
First interpolation filter
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10.6 Quadrature modulator and Numerically Controlled Oscillator (NCO)
The quadrature modulator allows the 14-bit I and Q data to be mixed with the carrier signal generated by the NCO. The frequency of the NCO is programmed over 32 bits and the sign of the sine component can be inverted in order to operate positive or negative, lower or upper single sideband up-conversion.
10.6.1 NCO in 32-bit
When using the NCO, the frequency can be set by the four registers FREQNCO_LSB, FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits. The frequency for the NCO in 32-bit is calculated as follows: M x fs f NCO = -------------32 2 where M is the decimal representation of FREQ_NCO[31:0]. The phase of the NCO can be set from 0 to 360 by both registers PHINCO_LSB and PHINCO_MSB over 16 bits. The default setting is fNCO = 96 MHz when fs = 640 Msps and the default phase is 0. (1)
10.6.2 Low-power NCO
When using the low-power NCO, the frequency can be set by the five MSBs of register FREQNCO_MSB. The frequency for the low-power NCO is calculated as follows: M x fs f NCO = -------------5 2 where M is the decimal representation of FREQ_NCO[31:27]. The phase of the low-power NCO can be set by the five MSBs of the register PHINCO_MSB. (2)
10.6.3 Minus_3dB
During normal use, a full-scale pattern will also be full scale at the output of the DAC. Nevertheless, when the I and Q data are simultaneously close to full scale, some clipping can occur and the Minus_3dB function can be used to reduce the gain in the modulator by 3 dB. This is to keep a full scale range at the output of the DAC without added interferers.
10.7 x / (sin x)
The roll-off effect of the DAC causes a selectable FIR filter to be inserted to compensate for the (sin x) / x effect. This filter introduces a DC loss of 3.4 dB. The coefficients are represented in Table 12 "Inversion filter coefficients".
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Inversion filter coefficients Upper H(9) H(8) H(7) H(6) Value 2 -4 10 -35 401
Table 12. Lower H(1) H(2) H(3) H(4) H(5)
First interpolation filter
10.8 DAC transfer function
The full scale output current for each DAC is the sum of the two complementary current outputs: I O ( fs ) = I IOUTP + I IOUTN The output current depends on the digital input data: DATA I IOUTP = I O ( fs ) x --------------- 16383 16383 - DATA I IOUTN = I O ( fs ) x ------------------------------------ 16383 (4) (3)
(5)
The setting applied to CODING (register 00h[2]; see Table 18 "Page 0 register allocation map") defines whether the DAC1408D650 operates with a binary input or a two's complement input. Table 13 shows the output current as a function of the input data, when IO(fs) = 20 mA.
Table 13. Data 0 ... 2048 ... 4095 DAC transfer function I13/Q13 to I0/Q0 Binary 00 0000 0000 0000 ... 10 0000 0000 0000 ... 11 1111 1111 1111 Two's complement 10 0000 0000 0000 ... 00 0000 0000 0000 ... 01 1111 1111 1111 0 mA ... 10 mA ... 20 mA 20 mA ... 10 mA ... 0 mA IOUTP IOUTN
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10.9 Full scale current
10.9.1 Regulation
The DAC1408D650 reference circuitry integrates an internal bandgap reference voltage which delivers a 1.25 V reference to the GAPOUT pin. It is recommended to decouple pin GAPOUT using a 100 nF capacitor. The reference current is generated via an external resistor of 909 (1 %) connected to pin VIRES. A control amplifier sets the appropriate full scale current (IO(fs)) for both DACs (see Figure 18).
REF. BANDGAP
100 nF
AGND
910 (1 %)
GAPOUT
AGND
VIRES
DAC CURRENT SOURCES ARRAY
001aaj816
Fig 18. Internal reference configuration
This configuration is optimum for temperature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor. 10.9.1.1 External regulation The DAC current can also be set by applying an external reference voltage to the non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage with GAP_PD (register 00h[0]; see Table 19 "COMMON register (address 00h) bit description").
10.9.2 Full scale current adjustment
The default full scale current (IO(fs)) is 20 mA but further adjustments can be made by the user to both DACs independently using the serial interface from 1.6 mA to 22 mA, 10 %. The settings applied to DAC_A_GAIN_COARSE[3:0] (register 0Ah; see Table 29 "DAC_A_CFG_2 register (address 0Ah) bit description" and register 0Bh; see Table 30 "DAC_A_CFG_3 register (address 0Bh) bit description") and DAC_B_GAIN COARSE[3:0] (register 0Dh; see Table 32 "DAC_B_CFG_2 register (address 0Dh) bit description" and register 0Eh; see Table 33 "DAC_B_CFG_3 register (address 0Eh) bit description") define the coarse variation of the full scale current (see Table 14).
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Table 14. IO(fs) coarse adjustment Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1.6 3.0 4.4 5.8 7.2 8.6 10.0 11.4 12.8 14.2 15.6 17.0 18.5 20.0 21.0 22.0 IO(fs) (mA)
The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see Table 29 "DAC_A_CFG_2 register (address 0Ah) bit description") and to DAC_B_GAIN_FINE[5:0] (register 0Dh; see Table 32 "DAC_B_CFG_2 register (address 0Dh) bit description") define the fine variation of the full scale current (see Table 15).
Table 15. IO(fs) fine adjustment Default settings are shown highlighted. DAC_GAIN_FINE[5:0] Decimal -32 ... 0 ... 31 Two's complement 10 0000 ... 00 0000 ... 01 1111 -10 % ... 0 ... +10 % Delta IO(fs)
The coding of the fine gain adjustment is two's complement.
10.10 Digital offset adjustment
When the DAC1408D650 analog output is DC connected to the next stage, the digital offset correction can be used to adjust the common mode level at the output of the DAC. It adds an offset at the end of the digital part, just before the DAC. The settings applied to DAC_A_OFFSET[11:0] (register 09h; see Table 28 "DAC_A_CFG_1 register (address 09h) bit description" and register 0Bh; see Table 30 "DAC_A_CFG_3 register (address 0Bh) bit description") and to "DAC_B_OFFSET[11:0]"
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(register 0Ch; see Table 31 "DAC_B_CFG_1 register (address 0Ch) bit description" and register 0Eh; see Table 33 "DAC_B_CFG_3 register (address 0Eh) bit description") define the range of variation of the digital offset (see Table 16).
Table 16. Digital offset adjustment Default settings are shown highlighted. DAC_OFFSET[11:0] Decimal -2048 -2047 ... -1 0 +1 ... +2046 +2047 Two's complement 1000 0000 0000 1000 0000 0001 ... 1111 1111 1111 0000 0000 0000 0000 0000 0001 ... 0111 1111 1110 0111 1111 1111 -4096 -4094 ... -2 0 +2 ... +4092 +4094 Offset applied
10.11 Analog output
The DAC1408D650 has two output channels each of which produces two complementary current outputs. These allow the even-order harmonics and noise to be reduced. The pins are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected via a load resistor RL to the 3.3 V analog power supply (VDDA(3V3)). For the equivalent analog output circuit of one DAC, refer to Figure 19. This circuit consists of a parallel combination of NMOS current sources, and their associated switches, for each segment.
VDDA(3V3)
RL
RL
IOUTAP/IOUTBP IOUTAN/IOUTBN
AGND
AGND
001aah019
Fig 19. Equivalent analog output circuit (one DAC)
The cascode source configuration increases the output impedance of the source, thus improving the dynamic performance of the DAC by introducing less distortion. The device can provide an output level of up to 2 Vo(p-p), depending on the application, the following stages and the targeted performances.
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DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.12 Auxiliary DACs
The DAC1408D650 integrates two auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a 10-bit resolution and are current sources (referenced to ground). I O ( AUX ) = I AUXP + I AUXN The output current depends on the auxiliary DAC data: AUX [ 9:0 ] AUXP = I O ( AUX ) x ------------------------ 1023 1023 - A UX [ 9:0 ] ) AUXN = I O ( AUX ) x ------------------------------------------ 1023 Table 17 shows the output current as a function of the auxiliary DAC data.
Table 17. Auxiliary DAC transfer function Default settings are shown highlighted. Data 0 ... 512 ... 1023 AUX[9:0] (binary) 00 0000 0000 ... 10 0000 0000 ... 11 1111 1111 IAUXP 0 mA ... 1.1 mA ... 2.2 mA IAUXN 2.2 mA ... 1.1 mA ... 0 mA
(6)
(7)
(8)
DAC1408D650
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.13 Output configuration
10.13.1 Basic output configuration
The use of a differentially-coupled transformer output provides optimum distortion performance (see Figure 20). In addition, it helps to match the impedance and provides electrical isolation.
VDDA(3V3)
50 2:1
0 mA to 20 mA IOUTnP 0 mA to 20 mA IOUTnN
50
50
VDDA(3V3) IOUTnP/IOUTnN; Vo(cm) = 2.8 V; Vo(dif)(p-p) = 1 V
001aaj817
Fig 20. 1 Vo(p-p) differential output with transformer
The DAC1408D650 can operate up to 2 Vo(p-p) differential outputs. In this configuration, it is recommended to connect the center tap of the transformer to a 62 resistor connected to the 3.3 V analog power supply, in order to adjust the DC common mode to approximately 2.7 V (see Figure 21).
VDDA(3V3)
100
VDDA(3V3)
62 4:1
0 mA to 20 mA IOUTnP 0 mA to 20 mA IOUTnN
100 50
VDDA(3V3) IOUTnP/IOUTnN; Vo(cm) = 2.7 V; Vo(dif)(p-p) = 2 V
001aaj818
Fig 21. 2 Vo(p-p) differential output with transformer
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.13.2 DC interface to an Analog Quadrature Modulator (AQM)
When the system operation requires to keep the DC component of the spectrum, the DAC1408D650 can use a DC interface to connect to an AQM. In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC. Figure 22 provides an example of a connection to an AQM with a 1.7 Vi(cm) common mode input level.
VDDA(3V3)
AQM (Vi(cm) = 1.7 V)
(1)
51.1
51.1 442
(2)
IOUTnP
442
BBP BBN 0 mA to 20 mA
768 768
IOUTnN
(1) IOUTnP/IOUTnN; V o(cm) = 2.67 V; Vo(dif)(p-p) = 1.98 V (2) BBP/BBN; V i(cm) = 1.7 V; Vi(dif)(p-p) = 1.26 V 001aaj541
Fig 22. An example of a DC interface to a 1.7 Vi(cm) AQM
Figure 23 provides an example of a connection to an AQM with a 3.3 Vi(cm) common mode input level.
VDDA(3V3)
5V
AQM (Vi(cm) = 3.3 V)
(1)
54.9
54.9 237
750
750
(2)
IOUTnP
237
BBP BBN
1.27 k 1.27 k
IOUTnN
(1) IOUTnP/IOUTnN; V o(cm) = 2.75 V; Vo(dif)(p-p) = 1.97 V (2) BBP/BBN; V i(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V 001aaj542
Fig 23. An example of a DC interface to a 3.3 Vi(cm) AQM
The auxiliary DACs can be used to control the offset in a precise range or with precise steps. Figure 24 provides an example of a DC interface with the auxiliary DACs to an AQM with a 1.7 Vi(cm) common mode input level.
DAC1408D650
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DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
VDDA(3V3)
AQM (Vi(cm) = 1.7 V)
(1)
51.1
51.1 442
(2)
IOUTnP
442
BBP BBN 0 mA to 20 mA
698 698
IOUTnN
AUXnP AUXnN 1.1 mA (typ.)
51.1 51.1
(1) IOUTnP/IOUTnN; V o(cm) = 2.67 V; Vo(dif)(p-p) = 1.94 V (2) BBP/BBN; V i(cm) = 1.7 V; Vi(dif)(p-p) = 1.23 V; offset correction up to 36 mV 001aaj543
Fig 24. An example of a DC interface to a 1.7 Vi(cm) AQM when using auxiliary DACs
Figure 25 provides an example of a DC interface with the auxiliary DACs to an AQM with a 3.3 Vi(cm) common mode input level.
VDDA(3V3)
5V
AQM (Vi(cm) = 3.3 V)
(1)
54.9
54.9 237
750
750
(2)
IOUTnP
237
BBP BBN
634 k 634 k
IOUTnN
AUXnP AUXnN
442 k 442 k
(1) IOUTnP/IOUTnN; V o(cm) = 2.75 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; V i(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V; offset correction up to 36 mV 001aaj544
Fig 25. An example of a DC interface to a 3.3 Vi(cm) AQM when using auxiliary DACs
The constraints to adjust the interface are the output compliance range of the DAC and the auxiliary DACs, the input common mode level of the AQM, and the range of offset correction.
DAC1408D650
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.13.3 AC interface to an Analog Quadrature Modulator (AQM)
When the AQM common mode voltage is close to ground, the DAC1408D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 26 provides an example of a connection to an AQM with a 0.5 Vi(cm) common mode input level when using auxiliary DACs.
VDDA(3V3)
5V
AQM (Vi(cm) = 0.5 V)
(1)
66.5
66.5 10 nF
2 k
2 k
(2)
IOUTnP
10 nF
BBP BBN 0 mA to 20 mA
174 174
IOUTnN
AUXnP AUXnN 1.1 mA (typ.)
34 34
(1) IOUTnP/IOUTnN; V o(cm) = 2.65 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; V i(cm) = 0.5 V; Vi(dif)(p-p) = 1.96 V; offset correction up to 70 mV 001aaj589
Fig 26. An example of an AC interface to a 0.5 Vi(cm) AQM when using auxiliary DACs
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.13.4 Phase correction
The Analog Quadrature Modulator which follows the DACs may have a phase imbalance which will result in undesired sideband. By adjusting the phase between the I and Q channels, the spur can be reduced. Without compensation the I and Q have a phase difference of /2 (90o). The registers Phasecorr_cntrl0 and Phasecorr_cntrl1 located in register page 0 allow a phase variation from 75,7o to 104,3o . The two registers define a signed value that range from -512 to +511. The resulting phase compensation (in radians) is given by the equation: Phasecorr_cntrl[9:0] / 2048.
10.14 Power and grounding
The power supplies should be decoupled with the following ground pins to optimize the decoupling:
* VDDA(1V8): pin 38 with pin 37; pin 44 with pin 43; pin 11 with pin 12; pin 17 with pin 18;
pin 32 with pin 31.
10.15 Configuration interface
10.15.1 Register description
DAC1408D650 implements indirect addressing using a page access method. The page-address is located at address 0x1F and is by default 0x00, which selects page 0 as default page. For example, to access registers which configure the JESDRX, one must first activate page 4 by writing 0x04 to the page-address 0x1F. The DAC1408D650 contains six different pages. The device has no embedded power-on-reset feature. Driving the RESET_N pin to set the device to its default state is mandatory.
10.15.2 Detailed descriptions of registers
The register information has been provided in page form accompanied by a detailed description for each bit in the tables following the register allocation map of each page.
DAC1408D650
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.15.2.1 Page 0 allocation map description
Table 18. Page 0 register allocation map R/W Bit definition b7 0 1 00h COMMON 01h TXCFG R/W R/W SPI_3W NCO_EN b6 SPI_RST NCO_ LOWPOWER_ SEL b5 INV_SINE_EN b4 b3 MODE[2:0] b2 DF b1 PD_ALL b0 PD_GAP INT_FIR[1:0] Default Bin Hex 10000100 84h 00000001 01h
Preliminary data sheet Rev. 02 -- 11 August 2010 38 of 98
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NXP Semiconductors
Address Register name
2 3 4 5 6 7 8 9
02h PLLCFG 03h FREQNCO_LSB 04h FREQNCO_LISB 05h FREQNCO_UISB 06h FREQNCO_MSB 07h PHINCO_LSB 08h PHINCO_MSB 09h DAC_A_CFG_1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PD_PLL
-
PLL_DIV[1:0] FREQ_NCO[7:0] FREQ_NCO[15:8] FREQ_NCO[23:16] FREQ_NCO[31:24] PHI_NCO[7:0] PHI_NCO[15:8]
PLL_PHASE_ SEL[1:0]
PLL_POL
00000000 00h 01100110 66h 01100110 66h 01100110 66h 00100110 26h 00000000 00h 00000000 00h 00000000 00h 01000000 40h 11000000 C0h 00000000 00h 01000000 40h 11000000 C0h
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
DAC_A_PD
DAC_A_SLEEP
DAC_A_OFFSET[5:0] DAC_A_GAIN_FINE[5:0] DAC_A_OFFSET[11:6] DAC_B_OFFSET[5:0] DAC_B_GAIN_FINE[5:0] DAC_B_OFFSET[11:6] DAC_DIG_BIAS[2:0] DAC_MST_BIAS[2:0] DAC_SLV_BIAS[2:0] DAC_CAS_BIAS[2:0] SEL_PH_FINE[1:0]
10 0Ah DAC_A_CFG_2 11 0Bh DAC_A_CFG_3 12 0Ch DAC_B_CFG_1 13 0Dh DAC_B_CFG_2 14 OEh DAC_B_CFG_3 15 OFh DAC_CFG
DAC_A_GAIN_COARSE[1:0] DAC_A_GAIN_COARSE[3:2] DAC_B_PD DAC_B_SLEEP DAC_B_GAIN_COARSE[1:0] DAC_B_GAIN_COARSE[3:2] DAC_DRV_BIAS[2:0] DAC_CK_BIAS[2:0] -
MINUS3DB NOISESHAPER 00000000 00h 00000110 06h 00000110 06h 01100110 66h 01100110 66h 00000010 02h 00000000 00h
17 11h DAC_CURRENT_0 R/W 18 12h DAC_CURRENT_1 R/W 19 13h DAC_CURRENT_2 R/W 20 14h DAC_CURRENT_3 R/W 21 15h DAC_SEL_PH_ FINE 22 16h PHASECORR_ CNTRL0 23 17h PHASECORR_ CNTRL1 R/W R/W
DAC1408D650
PHASE_CORR[7:0] DAC_A_AUX[9:2] PHASE_CORR[9:8]
R/W PHASE_CORR_ ENABLE
00000000 00h 10000000 80h
26 1Ah DAC_A_AUX_MSB R/W
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 18. Page 0 register allocation map ...continued R/W Bit definition b7 27 1Bh DAC_A_AUX_LSB R/W DAC_A_AUX_ PD 28 1Ch DAC_B_AUX_MSB R/W 29 1Dh DAC_B_AUX_LSB R/W DAC_B_AUX_ PD 31 1Fh PAGE_ADDRESS R/W b6 b5 b4 b3 DAC_B_AUX[9:2] PAGE[2:0] DAC_B_AUX[1:0] b2 b1 b0 DAC_A_AUX[1:0] Default Bin Hex 00000000 00h 10000000 80h 00000000 00h 00000000 00h
Preliminary data sheet Rev. 02 -- 11 August 2010 39 of 98
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NXP Semiconductors
Address Register name
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
DAC1408D650
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.15.2.2
Page 0 bit definition detailed description Please refer to Table 18 for a register overview for page 0. In the following tables, all the values emphasized in bold are the default values.
Table 19. COMMON register (address 00h) bit description Default settings are shown highlighted. Bit 7 Symbol SPI_3W Access R/W 0 1 6 SPI_RST R/W 0 1 2 DF R/W 0 1 1 PD_ALL R/W 0 1 0 GAP_PD R/W 0 1 Table 20. TXCFG register (address 01h) bit description Default settings are shown highlighted. Bit 7 Symbol NCO_EN Access R/W 0 1 6 NCO_LP_SEL R/W 0 1 5 INV_SINE_EN R/W 0 1 4 to 2 MODE[2:0] R/W 000 001 010 011 100 Value Description NCO disabled (the NCO phase is reset to 0) enabled low-power NCO NCO may use all 32 bits NCO frequency and phase given by the five MSBs of the registers 06h and 08h respectively x / (sin x) function disabled enabled modulation dual DAC: no modulation positive upper single sideband up-conversion positive lower single sideband up-conversion negative upper single sideband up-conversion negative lower single sideband up-conversion Value Description serial interface bus type 4 wire SPI 3 wire SPI serial interface reset no reset performs a reset on all registers except 0x00 data format unsigned format signed (two's compliment) format power-down no action all circuits (digital and analog) are switched off internal bandgap power-down no action internal bandgap references are switched off
DAC1408D650
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DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 20. TXCFG register (address 01h) bit description ...continued Default settings are shown highlighted. Bit 1 to 0 Symbol INT_FIR[1:0] Access R/W 00 01 10 11 Table 21. PLLCFG register (address 02h) bit description Default settings are shown highlighted. Bit 7 Symbol PLL_PD Access R/W 0 1 6 5 4 to 3 PLL_DIV[1:0] R/W R/W R/W 00 01 10 2 to 1 PLL_PHASE[1:0] R/W 00 01 10 11 0 PLL_POL R/W 0 1 Table 22. Bit 7 to 0 Table 23. Bit 7 to 0 FREQNCO_LSB register (address 03h) bit description Symbol FREQ_NCO[7:0] Access R/W Value 66h Description lower 8 bits for the NCO frequency setting 0 0 Value Description PLL switched on switched off undefined Must be written with '0' PLL divider factor 2 4 8 PLL phase shift of fs 0 120 240 undefined clock edge of DAC (fs) normal inverted Value Description interpolation no interpolation 2x 4x 8x
FREQNCO_LISB register (address 04h) bit description Symbol FREQ_NCO[15:8] Access R/W Value 66h Description lower intermediate 8 bits for the NCO frequency setting
Table 24. Bit 7 to 0
FREQNCO_UISB register (address 05h) bit description Symbol FREQ_NCO[23:16] Access R/W Value 66h Description upper intermediate 8 bits for the NCO frequency setting
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DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 25. Bit 7 to 0 Table 26. Bit 7 to 0 Table 27. Bit 7 to 0
FREQNCO_MSB register (address 06h) bit description Symbol FREQ_NCO[31:24] Access R/W Value 26h Description most significant 8 bits for the NCO frequency setting
PHINCO_LSB register (address 07h) bit description Symbol PH_NCO[7:0] Access R/W Value 00h Description lower 8 bits for the NCO phase setting
PHINCO_MSB register (address 08h) bit description Symbol PH_NCO[15:8] Access R/W Value 00h Description most significant 8 bits for the NCO phase setting
Table 28. DAC_A_CFG_1 register (address 09h) bit description Default settings are shown highlighted. Bit 7 Symbol DAC_A_PD Access R/W 0 1 6 DAC_A_SLEEP R/W 0 1 5 to 0 Table 29. Bit 7 to 6 5 to 0 DAC_A_OFFSET[5:0] R/W 00h Value Description DAC A power on off DAC A Sleep mode disabled enabled lower 6 bits for the DAC A offset
DAC_A_CFG_2 register (address 0Ah) bit description Symbol DAC_A_GAIN_COARSE[1:0] DAC_A_GAIN_FINE[5:0] Access R/W R/W Value 1h 00h Description least significant 2 bits for the DAC A gain setting for coarse adjustment lower 6 bits for the DAC A gain setting for fine adjustment
Table 30. Bit 7 to 6 5 to 0
DAC_A_CFG_3 register (address 0Bh) bit description Symbol DAC_A_GAIN_COARSE[3:2] DAC_A_OFFSET[11:6] Access R/W R/W Value 3h 00h Description most significant 2 bits for the DAC A gain setting for coarse adjustment most significant 6 bits for the DAC A offset
DAC1408D650
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DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 31. DAC_B_CFG_1 register (address 0Ch) bit description Default settings are shown highlighted. Bit 7 Symbol DAC_B_PD Access R/W 0 1 6 DAC_B_SLEEP R/W 0 1 5 to 0 Table 32. Bit 7 to 6 5 to 0 DAC_B_OFFSET[5:0] R/W 00h Value Description DAC B power on off DAC B Sleep mode disabled enabled lower 6 bits for the DAC B offset
DAC_B_CFG_2 register (address 0Dh) bit description Symbol DAC_B_GAIN_COARSE[1:0] DAC_B_GAIN_FINE[5:0] Access R/W R/W Value 1h 00h Description less significant 2 bits for the DAC B gain setting for coarse adjustment the 6 bits for the DAC B gain setting for fine adjustment
Table 33. Bit 7 to 6 5 to 0
DAC_B_CFG_3 register (address 0Eh) bit description Symbol DAC_B_GAIN_COARSE[3:2] DAC_B_OFFSET[11:6] Access R/W R/W Value 3h 00h Description most significant 2 bits for the DAC B gain setting for coarse adjustment most significant 6 bits for the DAC B offset
Table 34. DAC_CFG register (address 0Fh) bit description Default settings are shown highlighted. Bit 1 Symbol MINUS_3DB Access R/W 0 1 0 NOISE_SHAPER R/W 0 1 Table 35. DAC_CURRENT_0 register (address 11h) bit description Default settings are shown highlighted. Bit 3 to 1 Symbol DAC_DIG_BIAS[2:0] Access R/W Value 3h Description bias current control (see Table 47) Value Description NCO gain unity -3 dB noise shaper disabled enabled
Table 36. DAC_CURRENT_1 register (address 12h) bit description Default settings are shown highlighted. Bit 3 to 1 Symbol DAC_MST_BIAS[2:0] Access R/W Value 3h Description bias current control (see Table 47)
DAC1408D650
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 37. DAC_CURRENT_2 register (address 13h) bit description Default settings are shown highlighted. Bit 7 to 5 3 to 1 Symbol DAC_DRV_BIAS[2:0] DAC_SLV_BIAS[2:0] Access R/W R/W Value 3h 3h Description bias current control (see Table 47) bias current control (see Table 47)
Table 38. DAC_CURRENT_3 register (address 14h) bit description Default settings are shown highlighted. Bit 7 to 5 3 to 1 Symbol DAC_CK_BIAS[2:0] DAC_CAS_BIAS[2:0] Access R/W R/W Value 3h 3h Description bias current control (see Table 47) bias current control (see Table 47)
Table 39. DAC_SEL_PH_FINE register (address 15h) bit description Default settings are shown highlighted. Bit 1 to 0 Symbol SEL_PH_FINE[1:0] Access R/W Value 2h Description fine dac phase selection
Table 40. PHASECORR_CNTRL0 register (address 16h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol PHASE_CORR[7:0] Access R/W Value 00h Description lsb phase_correction_factor
Table 41. PHASECORR_CNTRL1 register (address 17h) bit description Default settings are shown highlighted. Bit 7 Symbol PHASE_CORR_ENABLE Access R/W 0 1 1 to 0 Table 42. Bit 7 to 0 PHASE_CORR[9:8] R/W 0h Value Description phase correction disabled enabled msb phase_correction_factor
DAC_A_AUX_MSB register (address 1Ah) bit description Symbol AUX_A[9:2] Access R/W Value 80h Description most significant 8 bits for the auxiliary DAC A
Table 43. DAC_A_AUX_LSB register (address 1Bh) bit description Default settings are shown highlighted. Bit 7 Symbol AUX_A_PD Access R/W 0 1 1 to 0 Table 44. Bit 7 to 0 AUX_A[1:0] R/W 0h Value Description auxiliary DAC A power on off lower 2 bits for the auxiliary DAC A
DAC_B_AUX_MSB register (address 1Ch) bit description Symbol AUX_B[9:2] Access R/W Value 80h Description most significant 8 bits for the auxiliary DAC B
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 45. DAC_B_AUX_LSB register (address 1Dh) bit description Default settings are shown highlighted. Bit 7 Symbol AUX_B_PD Access R/W 0 1 1 to 0 AUX_B[1:0] R/W 0h Value Description auxiliary DAC B power on off lower 2 bits for the auxiliary DAC B
Table 46. DAC_B_AUX_LSB register (address 1Dh) bit description Default settings are shown highlighted. Bit 2 to 0 Symbol PAGE[2:0] Access Value R/W 0h Description page address
Table 47. Bias current control table Default settings are shown highlighted. BIAS[2:0] 000 001 010 011 100 101 110 111 Deviation from nominal current -30 % ... ... 0% ... ... ... +30 %
DAC1408D650
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Preliminary data sheet
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.15.2.3 Page 1 allocation map description
Table 48. Page 1 register allocation map R/W Bit definition b7 0 1 2 3 00h MDS_MAIN R/W b6 b5 MDS_ RUN b4 MDS_NCO b3 MDS_SEL_ LN23 b2 MDS_32T_ ENA b1 MDS_ MASTER b0 MDS_ ENA MDS_EQCHECK[1:0] Default[1] Bin Hex 00000100 04h 10000000 80h 01000000 40h MDS_PULSEWIDTH[2:0] 00010000 10h
Preliminary data sheet Rev. 02 -- 11 August 2010 46 of 98
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NXP Semiconductors
Address Register name
01h MDS_WIN_PERIOD_A R/W 02h MDS_WIN_PERIOD_B R/W 03h MDS_MISCCNTRL0 R/W -
MDS_WIN_PERIOD_A[7:0] MDS_WIN_PERIOD_B[7:0] MDS_EVAL_ ENA MDS_ PRERUN_ ENA
4 5 6
04h MDS_MAN_ADJUSTD R/W LY 05h MDS_AUTO_CYCLES R/W 06h MDS_MISCCNTRL1 R/W
MDS_ MAN MDS_SR_ MDS_SR_ CKEN LOCKOUT EARLY LATE EQUAL MDS_ SR_ LOCK
MDS_MAN_ADJUSTDLY[6:0] MDS_AUTO_CYCLES[7:0] MDS_ RELOCK MDS_LOCK_DELAY[3:0]
01000000 40h 10000000 80h 00001111 0Fh
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
8 9
08h MDS_ADJDELAY 09h MDS_STATUS0
R R R R/W
MDS_ADJDELAY[6:0] MDS_LOCK EARLY_ ERROR JD_ODD LATE_ ERROR MDS_ PRERUN EQUAL_ FOUND MDS_ LOCKOUT PAGE[2:0] MDS_ ACTIVE MDS_ LOCK
uuuuuuuu uuh uuuuuuuu uuh uuuuuuuu uuh 00000000 00h
10 0Ah MDS_STATUS1 31 1Fh PAGE_ADDRESS
[1]
u = undefined at power-up or after reset.
DAC1408D650
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.15.2.4
Page 1 bit definition detailed description Please refer to Table 48 for a register overview and their default values. In the following tables, all the values emphasized in bold are the default values.
Table 49. MDS_MAIN register (address 00h) bit description Default settings are shown highlighted. Bit 7 to 6 Symbol MDS_EQCHECK[1:0] Access R/W 00 01 10 11 5 MDS_RUN R/W 0 1 4 MDS_NCO R/W 0 1 3 MDS_SEL_LN23 R/W 0 1 2 MDS_32T_ENA R/W 0 1 1 MDS_MASTER R/W 0 1 0 MDS_ENA R/W 0 1 Value Description lock mode lock when (early = 1 and late = 1) lock when (early = 1 and late = 1 and equal = 1) lock when equal = 1 force_lock (equal-check = 1) evaluation restart no action transition from 0 to 1 restarts evaluation_counter NCO synchronization no action NCO synchronization enabled synchronization reference use lane 1 enable as reference for synchronization use lane 2/lane 3 enable as reference for synchronization maximum delay maximum coarsedelay is 16T_dclk maximum coarsedelay is 32T_dclk MDS mode slave mode master mode MDS function disable MDS function enable MDS function
Table 50. MDS_WIN_PERIOD_A register (address 01h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol MDS_WIN_PERIOD_A[7:0] Access R/W Value 80h Description determines mds_window low-time
Table 51. MDS_WIN_PERIOD_B register (address 02h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol MDS_WIN_PERIOD_B[7:0] Access R/W Value 40h Description determines mds_window high-time
DAC1408D650
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Preliminary data sheet
Rev. 02 -- 11 August 2010
47 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 52. MDS_MISCCNTRL0 register (address 03h) bit description Default settings are shown highlighted. Bit 4 Symbol MDS_EVAL_ENA Access R/W 0 1 3 MDS_PRERUN_ENA R/W 0 1 2 to 0 MDS_PULSEWIDTH[2:0] R/W 000 001 010 to 111 Value Description mds_evaluation disabled enabled Automatic MDS start-up no mds_win/mds_ref generation in advance mds_win/mds_ref run-in before mds_evaluation width of MDS (in output clk-periods) 1T 2T (mds_pulsewidth -1) x 4T
Table 53. MDS_MAN_ADJUSTDLY register (address 04h) bit description Default settings are shown highlighted. Bit 7 Symbol MDS_MAN Access R/W 0 1 6 to 0 MDS_MAN_ADJUSTDLY[6:0] R/W 40h Value Description adjustment delays mode auto-control adjustment delays manual control adjustment delays adjustment delay value if MDS_MAN = 0 then initial value adjustment delay if MDS_MAN = 1 then controls adjustment delay
Table 54. MDS_AUTO_CYCLES register (address 05h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol MDS_AUTO_CYCLES[7:0] Access R/W Value 80h Description number of evaluation cycles applied for MDS
Table 55. MDS_MISCCNTRL1 register (address 06h) bit description Default settings are shown highlighted. Bit 7 Symbol MDS_SR_CKEN Access R/W 0 1 6 MDS_SR_LOCKOUT R/W 0 1 5 MDS_SR_LOCK R/W 0 1 Value Description lock mode free-running mds_cken mds_cken forced low lockout detector soft reset mds_lockout in use mds_lockout forced low lock detector soft reset mds_lock in use mds_lock forced low
DAC1408D650
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Preliminary data sheet
Rev. 02 -- 11 August 2010
48 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 55. MDS_MISCCNTRL1 register (address 06h) bit description ...continued Default settings are shown highlighted. Bit 4 Symbol MDS_RELOCK Access R/W 0 1 3 to 0 MDS_LOCK_DELAY[3:0] R/W Fh Value Description relock mode no action relock when lockout occurs number of succeeding 'equal'-detections until lock
Table 56. MDS_ADJDELAY register (address 08h) bit description Default settings are shown highlighted. Bit 6 to 0 Symbol MDS_ADJDELAY[6:0] Access R Value Description actual value adjustment delay
Table 57. MDS_STATUS0 register (address 09h) bit description Default settings are shown highlighted. Bit 7 Symbol EARLY Access R 0 1 6 LATE R 0 1 5 EQUAL R 0 1 4 MDS_LOCK R 0 1 3 EARLY_ERROR R 0 1 2 LATE_ERROR R 0 1 1 EQUAL_FOUND R 0 1 0 MDS_ACTIVE R 0 1 Value Description early signal (sampled) from early-late detector false true late signal (sampled) from early-late detector false true equal signal (sampled) from early-late detector false true result equal check false true adjustment delay maximum value stops the search false true adjustment delay minimum value stops the search false true eval_logic has detected equal condition false true eval_logic active false true
DAC1408D650
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Preliminary data sheet
Rev. 02 -- 11 August 2010
49 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 58. MDS_STATUS1 register (address 0Ah) bit description Default settings are shown highlighted. Bit 3 Symbol JD_ODD Access R 0 1 2 MDS_PRERUN R 0 1 1 MDS_LOCKOUT R 0 1 0 MDS_LOCK R 0 1 Table 59. PAGE_ADDRESS register (address 1Fh) bit description Default settings are shown highlighted. Bit 2 to 0 Symbol PAGE[2:0] Access R/W Value 0h Description page address Value Description MDS start mode mds start aligned to cdi-even sample mds start aligned to cdi-odd sample (only for ^2) MDS prerun phase active flag false true MDS lockout detected flag false true MDS lock flag false true
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
50 of 98
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.15.2.5 Page 2 allocation map description
Table 60. Page 2 register allocation map R/W Bit definition b7 0 00h MAINCONTROL R/W b6 b5 FULLRE_ INIT b4 SYNC_INIT_ LEVEL b3 0 b2 0 b1 b0 Default Bin Hex FORCE_ FORCE_ 00000011 03h RESET_ RESET_ DCLK FCLK FCLK_SEL[1:0] 00000000 00h 00111111 3Fh 00100000 20h 00011110 1Eh 00110010 32h 00110010 32h 00000100 04h SET_VCM[3:0] SET_SYNC_LEVEL[2:0] DUAL DAC_VERSION_ID[7:0] DIG_VERSION_ID[7:0] JRX_ANA_VERSION_ID[7:0] PAGE[2:0] DSP BIT_RES[1:0] 00000010 02h 01000011 43h 11011101 DDh 00000001 01h 00000010 02h 00000010 02h 00000000 00h
Preliminary data sheet Rev. 02 -- 11 August 2010 51 of 98
DAC1408D650 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
NXP Semiconductors
Address Register name
3 4 5 6 7 8 9
03h JCLK_CNTRL 04h RST_EXT_FCLK 05h RST_EXT_DCLK 07h PLL_CHARGETIME 08h PLL_RUN_IN_TIME 09h CA_RUN_IN_TIME
R/W R/W R/W R/W R/W R/W
SR_CDI
-
CDI_MODE[1:0]
-
FCLK_POL
RST_EXT_FCLK_TIME[7:0] RST_EXT_DCLK_TIME[7:0] DCSMU PREDIVIDER[7:0] PLL_CHARGE_TIME[7:0] PLL_RUNIN_TIME[7:0] CA_RUNIN_TIME[7:0] DAC SET_SYNC_VCOM[2:0] FRONTEND[1:0]
06h DCSMU_PREDIVCNT R/W
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
22 16h SET_VCM_VOLTAGE R/W 23 17h SET_SYNC 27 1Bh TYPE_ID 28 1Ch DAC_VERSION 29 1Dh DIG_VERSION 31 1Fh PAGE_ADDRESS R/W R R R R/W
30 1Eh JRX_ANA_VERSION R
DAC1408D650
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.15.2.6
Page 2 bit definition detailed description Please refer to Table 60 for a register overview and their default values. In the following tables, all the values emphasized in bold are the default values.
Table 61. MAINCONTROL register (address 00h) bit description Default settings are shown highlighted. Bit 5 Symbol FULL_RE_INIT Access R/W 1 0 4 SYNC_INIT_LEVEL R/W 0 1 3 2 1 FORCE_RESET_DCLK R/W R/W R/W 0 1 0 FORCE_RESET_FCLK R/W 0 1 Table 62. JCLK_CNTRL register (address 03h) bit description Default settings are shown highlighted. Bit 7 Symbol SR_CDI Access R/W 1 0 5 to 4 CDI_MODE[1:0] R/W 00 01 10 11 2 FCLK_POL R/W 0 1 1 to 0 FCLK_SEL[1:0] R/W 00 01 10 11 Value Description cdi reset soft reset cdi no action cdi mode cdi_mode 0 (^2 modes) cdi_mode 1 (^4 modes) cdi_mode 2 (^8 modes) reserved fclk polarity no action invert polarity fclk clock source dclk x 2 dclk dclk_div2; running dclk_div2; reset dclk_div2 divider Value Description initialization full re-initialization quick reinitialization synchronization synchronization starts with '0' synchronization starts with '1' must be written with '0' must be written with '0' reset_dclk release reset_dclk force reset_dclk reset_fclk release reset_fclk force reset_fclk
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
52 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 63. RST_EXT_FCLK register (address 04h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol RST_EXT_FCLK[7:0] Access R/W Value 3Fh Description specifies extension time reset_fclk in fclk periods
Table 64. RST_EXT_DCLK register (address 05h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol RST_EXT_DCLK[7:0] Access R/W Value 20h Description specifies extension time reset_dclk (in dclk-periods)
Table 65. DCSMU_PREDIVCNT register (address 06h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol DCSMU_PREDIVCNT[7:0] Access R/W Value 1Eh Description value used by dcsmu predivider (at fclk)
Table 66. PLL_CHARGETIME register (address 07h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol PLL_CHARGE_TIME[7:0] Access R/W Value 32h Description PLL charge time (at fclk/predivcnt; start-up)
Table 67. PLL_RUN_IN_TIME register (address 08h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol PLL_RUNIN_TIME[7:0] Access R/W Value 32h Description PLL run in time (at fclk/predivcnt; sel_pd)
Table 68. CA_RUN_IN_TIME register (address 09h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol CA_RUNIN_TIME[7:0] Access R/W Value 04h Description clock alignment run in time (at fclk/predivcnt)
Table 69. SET_VCM_VOLTAGE register (address 16h) bit description Default settings are shown highlighted. Bit 3 to 0 Symbol SET_VCM[3:0] Access R/W Value 02h Description set Vcm voltage level (see Table 76)
Table 70. SET_SYNC register (address 17h) bit description Default settings are shown highlighted. Bit 6 to 4 2 to 0 Symbol SET_SYNC_VCOM[2:0] SET_SYNC_LEVEL[2:0] Access R/W R/W Value 4h 3h Description set synchronization transmitter common-mode level (see Table 77) set synchronization transmitter output level swing (see Table 78)
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
53 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 71. TYPE_ID register (address 1Bh) bit description Default settings are shown highlighted. Bit 7 Symbol DAC Access R 0 1 6 to 5 FRONTEND [1:0] R 00 01 10 11 4 DUAL R 1 0 3 to 2 DSP R 00 01 10 11 1 to 0 BIT_RES[1:0] R 00 01 10 11 Table 72. DAC_VERSION register (address 1Ch) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol DAC_VERSION_ID[7:0] Access R Value 01h Description dual dac core version Value Description part type adc dac input format cmos lvds jesd204a reserved converter structure dual single digital processing none upfir ifssbm upfir + ifssbm resolution 16 bits 14 bits 12 bits 10 bits
Table 73. DIG_VERSION register (address 1Dh) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol DIG_VERSION_ID[7:0] Access R Value 02h Description digital version
Table 74. JRX_ANA_VERSION register (address 1Eh) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol JRX_ANA_VERSION_ID[7:0] Access R Value 02h Description analog deserializer version
Table 75. PAGE_ADDRESS register (address 1Fh) bit description Default settings are shown highlighted. Bit 2 to 0 Symbol PAGE[2:0] Access R/W Value 0h Description page address
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
54 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Lane common-mode voltage adjustment SET_VCM_VOLTAGE 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 SYNC common-mode voltage adjustment SET_SYNC_VCOM 111 110 101 100 011 010 001 000 SYNC swing voltage adjustment SET_SYNC_LEVEL 111 110 101 100 011 010 001 000
All information provided in this document is subject to legal disclaimers.
Table 76. Dec 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 77. Dec 7 6 5 4 3 2 1 0 Table 78. Dec 7 6 5 4 3 2 1 0
DAC1408D650
Register 16h: SET_VCM_VOLTAGE Vcom (V) 1.40 1.36 1.31 1.26 1.21 1.16 1.12 1.07 1.02 0.97 0.92 0.87 0.82 0.78 0.73 0.68
Register 17h: SET_SYNC Vcom (V) 1.46 1.36 1.27 1.17 1.07 0.98 0.88 0.79
Register 17h: SET_SYNC Vse (V) 0.48 0.42 0.36 0.30 0.24 0.18 0.12 0.06
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
55 of 98
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.15.2.7 Page 4 allocation map description
Table 79. Page 4 register allocation map R/W Bit definition b7 0 1 2 3 00h SR_DLP_0 01h SR_DLP_1 02h FORCE_LOCK 03h MAN_LOCK_ LN_1_0 05h CA_CNTRL 06h SCR-CNTRL 07h ILA_CNTRL 08h FORCE_ALIGN 09h MAN_ALIGN_ LN_0_1 R/W SR_SWA_ LN3 b6 SR_SWA_ LN2 b5 SR_SWA_ LN1 b4 b3 b2 b1 b0 Default Bin Hex SR_SWA_ SR_CA_LN3 SR_CA_LN2 SR_CA_LN1 SR_CA_LN0 00000000 00h LN0 SR_DEC_ LN2 SR_DEC_ LN1 SR_DEC_ 00000000 00h LN0 SR_ILA 00000000 00h 00000000 00h
Preliminary data sheet Rev. 02 -- 11 August 2010 56 of 98
DAC1408D650 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
NXP Semiconductors
Address Register name
R/W SR_CNTRL SR_CNTRL SR_CNTRL_ SR_CNTRL_ SR_DEC_ _LN3 _LN2 LN1 LN0 LN3 R/W R/W FORCE_ FORCE_ FORCE_ LOCK_LN3 LOCK_LN2 LOCK_LN1 MAN_LOCK_LN1[3:0] MAN_LOCK_LN3[3:0] FORCE_ LOCK_LN0 -
MAN_LOCK_LN0[3:0] MAN_LOCK_LN2[3:0]
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
4 5 6 7 8 9
04h MAN_LOCK_2_0 R/W R/W
00000000 00h
WORD_ WORD_ WORD_ WORD_ SELECT_RF SELECT_RF SELECT_RF SELECT_RF 00000000 00h SWAP_LN3 SWAP_LN2 SWAP_LN1 SWAP_LN0 _F10_LN3 _F10_LN2 _F10_LN1 _F10_LN0 FORCE_ SRC_LN3 FORCE_ SRC_LN2 FORCE_ SRC_LN1 SUP_LANE_ SYN DYN_ALIGN _ENA FORCE_ 00000000 00h SRC_LN0 EN_SCR FORCE_ ALIGN 10000011 83h 00000000 00h 00000000 00h 00000000 00h
R/W MAN_SCR MAN_SCR_ MAN_SCR_ MAN_SCR_ _LN3 LN2 LN1 LN0 R/W R/W R/W R/W R/W R/W R/W R/W R/W SEL_421_ 211 SEL_ILA[1:0] -
SEL_LOCK[2:0] -
MAN_ALIGN_LN1[3:0] MAN_ALIGN_LN3[3:0] SEL_KOUT_UNEXP_ LN23[1:0] SEL_KOUT_UNEXP_ LN10[1:0] SYNC_POL POL_LN3
MAN_ALIGN_LN0[3:0] MAN_ALIGN_LN2[3:0]
10 0Ah MAN_ALIGN_ LN_1_2 11 0Bh FA_ERR_ HANDLING
SEL_NIT_ERR_LN23[1:0] SEL_NIT_ERR_LN10[1:0] 00000000 00h SEL_SYNC[3:0] POL_LN2 POL_LN1 POL_LN0 00000000 00h 00000000 00h 11100100 E4h
DAC1408D650
12 0Ch SYNCOUT_ MODE 13 0Dh LANE_ POLARITY 14 OEh LANE_SELECT 16 10h SOFT_RESET_ SCRAMBLER
SEL_RE_INIT[2:0] -
LANE_SEL_LN3[1:0] -
LANE_SEL_LN2[1:0] -
LANE_SEL_LN1[1:0] SR_SCR_ LN3 SR_SCR_ LN2
LANE_SEL_LN0[1:0] SR_SCR_ LN1
SR_SCR_ 00000000 00h LN0 00000000 00h
17 11h INIT_SCR_S15T8 R/W _LN0
INIT_VALUE_S15_S8_LN0[7:0]
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 79. Page 4 register allocation map ...continued R/W Bit definition b7 18 12h INIT_SCR_ S7T1_LN0 19 13h INIT_SCR_ S15T8_LN1 20 14h INIT_SCR_ S7T1_LN1 21 15h INIT_SCR_ S15T8_LN2 22 16h INIT_SCR_ S7T1_LN2
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Preliminary data sheet Rev. 02 -- 11 August 2010 57 of 98
DAC1408D650
NXP Semiconductors
Address Register name
Default b5 b4 b3 b2 b1 b0 Bin Hex INIT_VALUE_S7_S1_LN0[6:0] INIT_VALUE_S15_S8_LN1[7:0] 00000000 00h 00000000 00h 00000000 00h 00000000 00h 00000000 00h
b6 -
R/W R/W R/W R/W R/W R/W R/W R/W
-
INIT_VALUE_S7_S1_LN1[6:0] INIT_VALUE_S15_S8_LN2[7:0]
-
INIT_VALUE_S7_S1_LN2[6:0] INIT_VALUE_S15_S8_LN3[7:0]
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
23 17h INIT_SCR_ S15T8_LN3 24 18h INIT_SCR_ S7T1_LN3 25 19h INIT_ILA_ BUFPTR_LN01 26 1Ah INIT_ILA_ BUFPTR_LN23 27 1Bh ERROR_ HANDLING 28 1Ch REINIT_CNTRL
00000000 00h 00000000 00h 10001000 88h 10001000 88h IGNORE_ 00000000 00h ERR
INIT_ILA_BUFPTR_LN1[3:0]
INIT_VALUE_S7_S1_LN3[6:0] INIT_ILA_BUFPTR_LN0[3:0] INIT_ILA_BUFPTR_LN2[3:0] IMPL_ALT
R/W INIT_ILA_BUFPTR_LN3[3:0] R/W R/W REINIT_ ILA_LN3 -
NAD_ERR_ KUX_CORR NAD_CORR CORR_MODE[1:0] CORR
REINIT_ILA REINIT_ILA_ REINIT_ILA_ RESYNC_O RESYNC_O RESYNC_O RESYNC_O 00000000 00h _LN2 LN1 LN0 _L_LN3 _L_LN2 _L_LN1 _L_LN0 PAGE[2:0] 00000000 00h
29 1Fh PAGE_ADDRESS R/W
DAC1408D650
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.15.2.8
Page 4 bit definition detailed description Please refer to Table 79 for a register overview and their default values. In the following tables, all the values emphasized in bold are the default values.
Table 80. SR_DLP_0 register (address 00h) bit description Default settings are shown highlighted. Bit 7 6 5 4 3 2 1 0 Symbol SR_SWA_LN3 SR_SWA_LN2 SR_SWA_LN1 SR_SWA_LN0 SR_CA_LN3 SR_CA_LN2 SR_CA_LN1 SR_CA_LN0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 0 0 0 0 0 0 0 0 Description softreset sync_word_alignment lane 3 softreset sync_word_alignment lane 2 softreset sync_word_alignment lane 1 softreset sync_word_alignment lane 0 softreset clock_alignment lane 3 softreset clock_alignment lane 2 softreset clock_alignment lane 1 softreset clock_alignment lane 0
Table 81. SR_DLP_1 register (address 01h) bit description Default settings are shown highlighted. Bit 7 6 5 4 3 2 1 0 Symbol SR_CNTRL_LN3 SR_CNTRL_LN2 SR_CNTRL_LN1 SR_CNTRL_LN0 SR_DEC_LN3 SR_DEC_LN2 SR_DEC_LN1 SR_DEC_LN0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 0 0 0 0 0 0 0 0 Description soft reset controller lane 3 soft reset controller lane 2 soft reset controller lane 1 soft reset controller lane 0 soft reset decoder_10b8b lane 3 soft reset decoder_10b8b lane 2 soft reset decoder_10b8b lane 1 soft reset decoder_10b8b lane 0
Table 82. FORCE_LOCK register (address 02h) bit description Default settings are shown highlighted. Bit 7 Symbol FORCE_LOCK_LN3 Access R/W 0 1 6 FORCE_LOCK_LN2 R/W 0 1 5 FORCE_LOCK_LN1 R/W 0 1 4 FORCE_LOCK_LN0 R/W 0 1 Value Description lane 3 lock mode automatic lock sync_word_alignment lane 3 manual lock sync_word_alignment lane 3 lane 2 lock mode automatic lock sync_word_alignment lane 2 manual lock sync_word_alignment lane 2 lane 1 lock mode automatic lock sync_word_alignment lane 1 manual lock sync_word_alignment lane 1 lane 0 lock mode automatic lock sync_word_alignment lane 0 manual lock sync_word_alignment lane 0
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
58 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 82. FORCE_LOCK register (address 02h) bit description ...continued Default settings are shown highlighted. Bit 0 Symbol SR_ILA Access R/W 0 1 Value Description soft reset interlane alignment no action reset
Table 83. MAN_LOCK_LN_1_0 register (address 03h) bit description Default settings are shown highlighted. Bit 7 to 4 3 to 0 Symbol MAN_LOCK_LN1[3:0] MAN_LOCK_LN0[3:0] Access R/W R/W Value 0h 0h Description manual lock setting synchronization word alignment lane 1 manual lock setting synchronization word alignment lane 0
Table 84. MAN_LOCK_2_0 register (address 04h) bit description Default settings are shown highlighted. Bit 7 to 4 3 to 0 Symbol MAN_LOCK_LN3[3:0] MAN_LOCK_LN2[3:0] Access R/W R/W Value 0h 0h Description manual lock setting synchronization word alignment lane 3 manual lock setting synchronization word alignment lane 2
Table 85. Bit 7
CA_CNTRL register (address 05h) bit description Symbol WORD_SWAP_LN3 Access R/W 0 1 Value Description lane 3 bit swapping dout_ca_ln3[7:0] = din_ca_ln3[7:0] dout_ca_ln3[7:0] = din_ca_ln3[0:7] lane 2 bit swapping 0 1 dout_ca_ln2[7:0] = din_ca_ln2[7:0] dout_ca_ln2[7:0] = din_ca_ln2[0:7] lane 1 bit swapping 0 1 dout_ca_ln1[7:0] = din_ca_ln1[7:0] dout_ca_ln1[7:0] = din_ca_ln1[0:7] lane 0 bit swapping 0 1 dout_ca_ln0[7:0] = din_ca_ln0[7:0] dout_ca_ln0[7:0] = din_ca_ln0[0:7] lane 3 sampling mode 0 1 din_ca_ln3 sampled at falling edge f10_ln3 din_ca_ln3 sampled at rising edge f10_ln3 lane 2 sampling mode 0 1 din_ca_ln2 sampled at falling edge f10_ln2 din_ca_ln2 sampled at rising edge f10_ln2
6
WORD_SWAP_LN2
R/W
5
WORD_SWAP_LN1
R/W
4
WORD_SWAP_LN0
R/W
3
SELECT_RF_F10_LN3
R/W
2
SELECT_RF_F10_LN2
R/W
DAC1408D650
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
59 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 85. Bit 1
CA_CNTRL register (address 05h) bit description ...continued Symbol SELECT_RF_F10_LN1 Access R/W 0 1 Value Description lane 1 sampling mode din_ca_ln1 sampled at falling edge f10_ln1 din_ca_ln1 sampled at rising edge f10_ln1 lane 0 sampling mode 0 1 din_ca_ln0 sampled at falling edge f10_ln0 din_ca_ln0 sampled at rising edge f10_ln0
0
SELECT_RF_F10_LN0
R/W
Table 86. Bit 7
SCR-CNTRL register (address 06h) bit description Symbol MAN_SCR_LN3 Access R/W 0 1 Value Description lane 3 manual scrambling scrambling lane 3 off (when force_scr_ln3 = 1) scrambling lane 3 on (when force_scr_ln3 = 1) lane 2 manual scrambling 0 1 scrambling lane 2 off (when force_scr_ln2 = 1) scrambling lane 2 on (when force_scr_ln2 = 1) lane 1 manual scrambling 0 1 scrambling lane 1 off (when force_scr_ln1 = 1) scrambling lane 1 on (when force_scr_ln1 = 1) lane 0 manual scrambling 0 1 scrambling lane 0 off (when force_scr_ln0 = 1) scrambling lane 0 on (when force_scr_ln0 = 1) lane 3 scrambling mode 0 1 scrambling lane 3 depends on lock_ln3 and en_scr scrambling lane 3 depends on man_scr_ln3 lane 2 scrambling mode 0 1 scrambling lane 2 depends on lock_ln2 and en_scr scrambling lane 2 depends on man_scr_ln2 lane 1 scrambling mode 0 1 scrambling lane 1 depends on lock_ln1 and en_scr scrambling lane 1 depends on man_scr_ln1 lane 0 scrambling mode 0 1 scrambling lane 0 depends on lock_ln0 and en_scr scrambling lane 0 depends on man_scr_ln0
6
MAN_SCR_LN2
R/W
5
MAN_SCR_LN1
R/W
4
MAN_SCR_LN0
R/W
3
FORCE_SRC_LN3
R/W
2
FORCE_SRC_LN2
R/W
1
FORCE_SRC_LN1
R/W
0
FORCE_SRC_LN0
R/W
DAC1408D650
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Preliminary data sheet
Rev. 02 -- 11 August 2010
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 87. Bit 7
ILA_CNTRL register (address 07h) bit description Symbol SEL_421_211 Access R/W 0 1 Value Description inter-lane alignment mode inter-lane alignment based on lane 3 : lane 2 and/or lane 1 : lane 0 inter-lane alignment based on ln3:ln0 inter-lane alignment trigger mode 00 01 10 11 inter-lane alignment is done after receiving 1 /A/-symbol inter-lane alignment is done after receiving 2 /A/-symbols inter-lane alignment is done after receiving 3 /A/-symbols inter-lane alignment is done after receiving 4 /A/-symbols inter-lane alignment start mode 000 001 010 011 100 101 inter-lane alignment may start only if all (4 or 2) lanes are locked inter-lane alignment may start if one of the (4 or 2) lanes are locked inter-lane alignment may start if lane 0 is locked inter-lane alignment may start if lane 1 is locked inter-lane alignment may start if lane 2 is locked inter-lane alignment may start if lane 3 is locked inter-lane alignment enable 0 1 inter-lane alignment synchronization disabled inter-lane alignment synchronization enabled data descrambling 0 1 data descrambling disabled enabled
6 to 5
SEL_ILA[1:0]
R/W
4 to 2
SEL_LOCK[2:0]
R/W
1
SUP_LANE_SYN
R/W
0
EN_SCR
R/W
Table 88. Bit 1
FORCE_ALIGN register (address 08h) bit description Symbol DYN_ALIGN_ENA Access R/W 0 1 Value Description dynamic re-alignment mode no dynamic re-alignment dynamic re-alignment (and monitoring) enabled lane alignment mode 0 1 automatic lane alignment based on /A/-symbols manual lane alignment based on man_align_lnx
0
FORCE_ALIGN
R/W
Table 89. Bit 7 to 4 3 to 0
DAC1408D650
MAN_ALIGN_LN_0_1 register (address 09h) bit description Symbol MAN_ALIGN_LN1[3:0] MAN_ALIGN_LN0[3:0] Access R/W R/W Value 00h 00h Description indicates alignment data-delay for lane 1 [1..15] indicates alignment data-delay for lane 0 [1..15]
(c) NXP B.V. 2010. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Preliminary data sheet
Rev. 02 -- 11 August 2010
61 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 90. Bit 7 to 4 3 to 0
MAN_ALIGN_LN_2_3 register (address 0Ah) bit description Symbol MAN_ALIGN_LN3[3:0] MAN_ALIGN_LN2[3:0] Access R/W R/W Value 00h 00h Description indicates alignment data-delay for lane 3 [1..15] indicates alignment data-delay for lane 2 [1..15]
Table 91. FA_ERR_HANDLING register (address 0Bh) bit description Default settings are shown highlighted. Bit 7 to 6 Symbol SEL_KOUT_ UNEXP_LN23[1:0] Access R/W 00 01 10 11 5 to 4 SEL_KOUT_ UNEXP_LN10[1:0] R/W 00 01 10 11 3 to 2 SEL_NIT_ERR_ LN23[1:0] R/W 00 01 10 11 1 to 0 SEL_NIT_ERR_ LN10[1:0] R/W 00 01 10 11 Value Description lane 2/lane 3 unexpected /K/ error handling error_handling i.c.o. unexpected /K/ in lane 2 or lane 3 error_handling i.c.o. unexpected /K/ in lane 2 and lane 3 error_handling i.c.o. unexpected /K/ in lane 2 error_handling i.c.o. unexpected /K/ in lane 3 lane 0/lane 1 unexpected /K/ error handling error_handling i.c.o. unexpected /K/ in lane 0 or lane 1 error_handling i.c.o. unexpected /K/ in lane 0 and lane 1 error_handling i.c.o. unexpected /K/ in lane 0 error_handling i.c.o. unexpected /K/ in lane 1 lane 2/lane 3 nit-error handling error_handling i.c.o. nit-errors in lane 2 or lane 3 error_handling i.c.o. nit-errors lane 2 and lane 3 error_handling i.c.o. nit-errors in lane 2 error_handling i.c.o. nit-errors in lane 3 lane 0/lane 1 not-error handling error_handling i.c.o. nit-errors in lane 0 or lane 1 error_handling i.c.o. nit-errors lane 0 and lane 1 error_handling i.c.o. nit-errors in lane 0 error_handling i.c.o. nit-errors in lane 1
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
62 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 92. SYNCOUT_MODE register (address 0Ch) bit description Default settings are shown highlighted. Bit 7 to 5 Symbol SEL_RE_INIT[2:0] Access R/W 000 001 010 011 100 101 110 111 4 SYNC_POL R/W 0 1 3 to 0 SEL_SYNC[3:0] R/W 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 other Table 93. Bit 3 LANE_POLARITY register (address 0Dh) bit description Symbol POL_LN3 Access R/W 0 1 2 POL_LN2 R/W 0 1 1 POL_LN1 R/W 0 1 0 POL_LN0 R/W 0 1
DAC1408D650
Value
Description reinitialization mode i_re_init when 1 of the lane_rst's is active i_re_init when rst_ln0 or rst_ln1 is active i_re_init when rst_ln2 or rst_ln3 is active i_re_init when rst_ln0 is active i_re_init when rst_ln1 is active i_re_init when rst_ln2 is active i_re_init when rst_ln3 is active i_re_init remains '0' synchronization polarity sync_out is active when low sync_out is active when high synchronization mode sync when one of the four lane_syncs is active sync when all four lane_syncs are active sync when sync_ln0 or sync_ln1 is active sync when both sync_ln0 and sync_ln1 are active sync when sync_ln2 or sync_ln3 is active sync when both sync_ln2 and sync_ln3 are active sync when sync_ln0 is active sync when sync_ln1 is active sync when sync_ln2 is active sync when sync_ln3 is active sync remains fixed '1' sync remains fixed '0'
Value
Description lane 3 data polarity no action invert all databits of dout_ca_ln3[7:0] lane 2 data polarity no action invert all databits of dout_ca_ln2[7:0] lane 1 data polarity no action invert all databits of dout_ca_ln1[7:0] lane 0 data polarity no action invert all databits of dout_ca_ln0[7:0]
(c) NXP B.V. 2010. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Preliminary data sheet
Rev. 02 -- 11 August 2010
63 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 94. LANE_SELECT register (address 0Eh) bit description Default settings are shown highlighted. Bit 7 to 6 Symbol LANE_SEL_LN3[1:0] Access R/W 00 01 10 11 5 to 4 LANE_SEL_LN2[1:0] R/W 00 01 10 11 3 to 2 LANE_SEL_LN1[1:0] R/W 00 01 10 11 1 to 0 LANE_SEL_LN0[1:0] R/W 00 01 10 11 Table 95. Bit 3 Value Description lane 3 data mapping ila_in_ln3 = lane_ln0 (dout and controls) ila_in_ln3 = lane_ln1 (dout and controls) ila_in_ln3 = lane_ln2 (dout and controls) ila_in_ln3 = lane_ln3 (dout and controls) lane 2 data mapping ila_in_ln2 = lane_ln0 (dout and controls) ila_in_ln2 = lane_ln1 (dout and controls) ila_in_ln2 = lane_ln2 (dout and controls) ila_in_ln2 = lane_ln3 (dout and controls) lane 1 data mapping ila_in_ln1 = lane_ln0 (dout and controls) ila_in_ln1 = lane_ln1 (dout and controls) ila_in_ln1 = lane_ln2 (dout and controls) ila_in_ln1 = lane_ln3 (dout and controls lane 0 data mapping ila_in_ln0 = lane_ln0 (dout and controls) ila_in_ln0 = lane_ln1 (dout and controls) ila_in_ln0 = lane_ln2 (dout and controls) ila_in_ln0 = lane_ln3 (dout and controls)
SOFT_RESET_SCRAMBLER register (address 10h) bit description Symbol SR_SCR_LN3 Access R/W 0 1 Value Description lane 3 scrambler reset no action soft_reset scrambler of lane0 lane 2 scrambler reset 0 1 no action soft_reset scrambler of lane1 lane 1 scrambler reset 0 1 no action soft_reset scrambler of lane2 lane 0 scrambler reset 0 1 no action soft_reset scrambler of lane3
2
SR_SCR_LN2
R/W
1
SR_SCR_LN1
R/W
0
SR_SCR_LN0
R/W
Table 96. Bit 7 to 0
INIT_SCR_S15T8_LN0 register (address 11h) bit description Symbol INIT_VALUE_S15_S8_LN0[7:0] Access R/W Value 00h Description initialization value for lane 0 descrambler bits s15 : s8
DAC1408D650
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Preliminary data sheet
Rev. 02 -- 11 August 2010
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 97. Bit 6 to 0 Table 98. Bit 7 to 0
INIT_SCR_S7T1_LN0 (address 12h) bit description Symbol INIT_VALUE_S7_S1_LN0[6:0] Access R/W Value 00h Description initialization value for lane 0 descrambler bits s7 : s1
INIT_SCR_S15T8_LN1 register (address 13h) bit description Symbol INIT_VALUE_S15_S8_LN1[7:0] Access R/W Value 00h Description initialization value for lane 1 descrambler bits s15 : s8
Table 99. Bit 6 to 0
INIT_SCR_S7T1_LN1 register (address 14h) bit description Symbol INIT_VALUE_S7_S1_LN1[6:0] Access R/W Value 00h Description initialization value for lane 1 descrambler bits s7 : s1
Table 100. INIT_SCR_S15T8_LN2 register (address 15h) bit description Bit 7 to 0 Symbol INIT_VALUE_S15_S8_LN2[7:0] Access R/W Value 00h Description initialization value for lane 2 descrambler bits s15 : s8
Table 101. INIT_SCR_S7T1_LN2 register (address 16h) bit description Bit 6 to 0 Symbol INIT_VALUE_S7_S1_LN2[6:0] Access R/W Value 00h Description initialization value for lane 2 descrambler bits s7 : s1
Table 102. INIT_SCR_S15T8_LN3 register (address 17h) bit description Bit 7 to 0 Symbol INIT_VALUE_S15_S8_LN3[7:0] Access R/W Value 00h Description initialization value for lane 3 descrambler bits s15 : s8
Table 103. INIT_SCR_S7T1_LN3 register (address 18h) bit description Bit 6 to 0 Symbol INIT_VALUE_S7_S1_LN3[6:0] Access R/W Value 00h Description initialization value for lane 3 descrambler bits s7 : s1
Table 104. INIT_ILA_BUFPTR_LN01 register (address 19h) bit description Bit 7 to 4 3 to 0 Symbol INIT_ILA_BUFPTR_LN1[3:0] INIT_ILA_BUFPTR_LN0[3:0] Access R/W R/W Value 8h 8h Description initialization value for ila bufptr lane 1 initialization value for ila bufptr lane 0
Table 105. INIT_ILA_BUFPTR_LN23 register (address 1Ah) bit description Bit 7 to 4 3 to 0 Symbol INIT_ILA_BUFPTR_LN3[3:0] INIT_ILA_BUFPTR_LN2[3:0] Access R/W R/W Value 8h 8h Description initialization value for ila bufptr lane 3 initialization value for ila bufptr lane 2
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
65 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 106. ERROR_HANDLING register (address 1Bh) bit description Default settings are shown highlighted. Bit 6 Symbol NAD_ERR_CORR Access R/W 0 1 5 KUX_CORR R/W 0 1 4 NAD_CORR R/W 0 1 3 to 2 CORR_MODE[1:0] R/W 00 01 10 11 1 IMPL_ALT R/W 0 1 0 IGNORE_ERR R/W 0 1 Table 107. REINIT_CNTRL register (address 1Ch) bit description Default settings are shown highlighted. Bit 7 Symbol REINIT_ILA_LN3 Access R/W 0 1 6 REINIT_ILA_LN2 R/W 0 1 5 REINIT_ILA_LN1 R/W 0 1 4 REINIT_ILA_LN0 R/W 0 1 Value Description lane 3, ila-buffer out-of-range check no action lane 3 ila-buffer out-of-range_error will activate reinitialization lane 2, ila-buffer out-of-range check no action lane 2 ila-buffer out-of-range_error will activate reiniializationt lane 1, ila-buffer out-of-range check no action lane 1 ila-buffer out-of-range_error will activate reinitialization lane 0, ila-buffer out-of-range check no action lane 0 ila-buffer out-of-range_error will activate reinitialization Value Description frame assembler (fa) nit-errors passed to fa nad (nit and disparity) errors passed to fa k-character error mode unexpected k-character errors ignored (at fa) unexpected k-character errors concealment (at fa) nad error mode nad-errors ignored (at fa) nad-errors concealment (at fa) conceal mode conceal 1 period at fa conceal 2 periods at fa conceal 3 periods at fa conceal 4 periods at fa disparity error detection configuration default disparity error detection (table mode) alternative disparity error detection (cnt mode) general error mode no action ignore disparity/nit-errors at lane-controller
DAC1408D650
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(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
66 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 107. REINIT_CNTRL register (address 1Ch) bit description ...continued Default settings are shown highlighted. Bit 3 Symbol RESYNC_O_L_LN3 Access R/W 0 1 2 RESYNC_O_L_LN2 R/W 0 1 1 RESYNC_O_L_LN1 R/W 0 1 0 RESYNC_O_L_LN0 R/W 0 1 Table 108. PAGE_ADDRESS register (address 1Fh) bit description Bit 2 to 0 Symbol PAGE[2:0] Access R/W Value 0h Description page_address Value Description lane 3, resync over link no action lane 3 lane controller checks for k28.5 /K/-symbols lane 2, resync over link no action lane 2 lane controller checks for k28.5 /K/-symbols lane 1, resync over link no action lane 1 lane controller checks for k28.5 /K/-symbols lane 0, resync over link no action ln0 lane controller checks for k28.5 /K/-symbols
DAC1408D650
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
67 of 98
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.15.2.9 Page 5 allocation map description
Table 109. Page 5 register allocation map Address Register name 0 1 2 3 4 00h ILA_MON_1_0 01h ILA_MON_3_2 02h ILA_BUF_ERR 03h CA_MON 04h DEC_FLAGS R/W Bit definition b7 R R R R R b6 b5 ILA_MON_LN1[3:0] ILA_MON_LN3[3:0] ILA_BUF_ ERR_LN3 b4 b3 b2 b1 ILA_MON_LN0[3:0 ILA_MON_LN2[3:0] ILA_BUF_ ERR_LN2 ILA_BUF_ ERR_LN1 ILA_BUF_ ERR_LN0 b0 Default[1] Bin Hex uuuuuuuu uuh uuuuuuuu uuh uuuuuuuu uuh uuuuuuuu uuh
Preliminary data sheet Rev. 02 -- 11 August 2010 68 of 98
DAC1408D650 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
NXP Semiconductors
CA_MON_LN3[1:0]
CA_MON_LN2[1:0] DEC_NIT_ ERR_LN0 K28_7_LN0 K28_7_LN1 K28_7_LN2 K28_7_LN3 -
CA_MON_LN1[1:0]
CA_MON_LN0[1:0]
DEC_NIT DEC_NIT DEC_NIT_ _ERR_ _ERR_ ERR_LN1 LN3 LN2 -
DEC_DISP_ DEC_DISP_ DEC_DISP_ DEC_DISP_ uuuuuuuu uuh ERR_LN3 ERR_LN2 ERR_LN1 ERR_LN0
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
5 6 7 8 9
05h KOUT_FLAG
R
DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ uuuuuuuu uuh LN3 LN2 LN1 LN0 K28_5_LN0 K28_5_LN1 K28_5_LN2 K28_5_LN3 K28_4_LN0 K28_4_LN1 K28_4_LN2 K28_4_LN3 K28_3_LN0 K28_3_LN1 K28_3_LN2 K28_3_LN3 K28_0_LN0 uuuuuuuu uuh K28_0_LN1 uuuuuuuu uuh K28_0_LN2 uuuuuuuu uuh K28_0_LN3 uuuuuuuu uuh
06h K28_LN0_FLAG R 07h K28_LN1_FLAG R 08h K28_LN2_FLAG R 09h K28_LN3_FLAG R
10 0Ah KOUT_ R UNEXPECTED_ FLAG 11 0Bh LOCK_CNT_ MON_LN01 R R
DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ uuuuuuuu uuh UNEXP_LN3 UNEXP_LN2 UNEXP_LN1 UNEXP_LN0 LOCK_CNT_MON_LN0[3:0] LOCK_CNT_MON_LN2[3:0] CS_STATE_LN1[1:0] CS_STATE_LN0[1:0] uuuuuuuu uuh uuuuuuuu uuh uuuuuuuu uuh 00000000 00h
LOCK_CNT_MON_LN1[3:0] LOCK_CNT_MON_LN3[3:0] CS_STATE_LN3[1:0] RST_ BUF_ ERR_ FLAGS CS_STATE_LN2[1:0] -
12 0Ch LOCK_CNT_ MON_LN23
13 0Dh CS_STATE_LNX R 14 0Eh RST_BUF_ERR_ R/W FLAGS
DAC1408D650
15 0Fh INTR_MISC_ ENA
R/W
INTR_ INTR_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ 00000000 00h ENA_ ENA_CS_ CS_INIT_ CS_INIT_ BUF_ERR_ BUF_ERR_ BUF_ERR_ BUF_ERR_ CS_ INIT_LN2 LN1 LN0 LN3 LN2 LN1 LN0 INIT_LN3 FLAG_CNT_LN0[7:0] uuuuuuuu uuh
16 10h FLAG_CNT_LSB R _LN0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 109. Page 5 register allocation map ...continued Address Register name 17 11h FLAG_CNT_ MSB_LN0 R/W Bit definition b7 R b6 b5 b4 b3 b2 b1 b0 FLAG_CNT_LN0[15:8] FLAG_CNT_LN1[7:0] FLAG_CNT_LN1[15:8] FLAG_CNT_LN2[7:0] FLAG_CNT_LN2[15:8] FLAG_CNT_LN3[7:0] FLAG_CNT_LN3[15:8] BER_LEVEL[7:0] BER_LEVEL[15:8] INTR_ ENA_ NIT RST_ CFC_ LN1 INTR_ ENA_ DISP Default[1] Bin Hex uuuuuuuu uuh uuuuuuuu uuh uuuuuuuu uuh uuuuuuuu uuh uuuuuuuu uuh
Preliminary data sheet Rev. 02 -- 11 August 2010 69 of 98
DAC1408D650 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
NXP Semiconductors
18 12h FLAG_CNT_LSB R _LN1 19 13h FLAG_CNT_ MSB_LN1 R
20 14h FLAG_CNT_LSB R _LN2 21 15h FLAG_CNT_ MSB_LN2 R
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
22 16h FLAG_CNT_LSB R _LN3 23 17h FLAG_CNT_ MSB_LN3 24 18h BER_LEVEL_ LSB 25 19h BER_LEVEL_ MSB 26 1Ah INTR_ENA R R/W R/W R/W
uuuuuuuu uuh uuuuuuuu uuh 00000000 00h 00000000 00h
INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ 00000000 00h KOUT KOUT_ K28_7 K28_5 K28_3 MISC UNEXP SEL_CFC_LN1[2:0] RST_CFC_ LN0 RST_CFC_ LN2 SEL_CFC_LN0[2:0] 01010101 55h
27 1Bh CNTRL_ R/W FLAGCNT_LN01
28 1Ch CNTRL_ R/W RST_ FLAGCNT_LN23 CFC_LN3 29 1Dh MON_FLAGS_ RESET R/W RST_NIT _ERRFLAGS BER_ MODE RST_ DISP_ ERR_ FLAGS INTR_ CLEAR -
SEL_CFC_LN3[2:0]
SEL_CFC_LN2[2:0]
01010101 55h
DAC1408D650
RST_KOUT RST_KOUT RST_K28_ RST_K28_ RST_K28_ RST_K28_ 00000000 00h _FLAGS _UNEXPEC LN3_FLAGS LN2_FLAGS LN1_FLAGS LN0_FLAGS TED_FLAGS INTR_MODE[2:0] PAGE[2:0] 00000000 00h 00000000 00h
30 1Eh DBG_CNTRL 31 1Fh PAGE_ ADDRESS
[1]
R/W R/W
u = undefined at power-up or after reset.
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.15.2.10
Page 5 bit definition detailed description Please refer to Table 109 for a register overview and their default values. In the following tables, all the values emphasized in bold are the default values.
Table 110. ILA_MON_1_0 register (address 00h) bit description Default settings are shown highlighted. Bit 7 to 4 3 to 0 Symbol ILA_MON_LN1[3:0] ILA_MON_LN0[3:0] Access R R Value Description ila_buf_ln1 pointer ila_buf_ln0 pointer
Table 111. ILA_MON_3_2 register (address 01h) bit description Default settings are shown highlighted. Bit 7 to 4 3 to 0 Symbol ILA_MON_LN3[3:0] ILA_MON_LN2[3:0] Access R R Value Description ila_buf_ln3 pointer ila_buf_ln2 pointer
Table 112. ILA_BUF_ERR register (address 02h) bit description Default settings are shown highlighted. Bit 3 Symbol ILA_BUF_ERR_LN3 Access R 0 1 2 ILA_BUF_ERR_LN2 R 0 1 1 ILA_BUF_ERR_LN1 R 0 1 0 ILA_BUF_ERR_LN0 R 0 1 Table 113. CA_MON register (address 03h) bit description Default settings are shown highlighted. Bit 7 to 6 5 to 4 3 to 2 1 to 0 Symbol CA_MON_LN3[1:0] CA_MON_LN2[1:0] CA_MON_LN1[1:0] CA_MON_LN0[1:0] Access R R R R Value Description clock alignment phase monitor lane 3 clock alignment phase monitor lane 2 clock alignment phase monitor lane 1 clock alignment phase monitor lane 0 Value Description lane 3 ila buffer error ila_buf_ln3 pointer is in range ila_buf_ln3 pointer is out of range lane 2 ila buffer error ila_buf_ln2 pointer is in range ila_buf_ln2 pointer is out of range lane 1 ila buffer error ila_buf_ln1 pointer is in range ila_buf_ln1 pointer is out of range lane 0 ila buffer error ila_buf_ln0 pointer is in range ila_buf_ln0 pointer is out of range
DAC1408D650
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
70 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 114. DEC_FLAGS register (address 04h) bit description Bit 7 6 5 4 3 2 1 0 Symbol DEC_NIT_ERR_LN3 DEC_NIT_ERR_LN2 DEC_NIT_ERR_LN1 DEC_NIT_ERR_LN0 DEC_DISP_ERR_LN3 DEC_DISP_ERR_LN2 DEC_DISP_ERR_LN1 DEC_DISP_ERR_LN0 Access R R R R R R R R Value Description not-in-table-errorflag lane 3 not-in-table-errorflag lane 2 not-in-table-errorflag lane 1 not-in-table-errorflag lane 0 disparity-errorflag lane 3 disparity-errorflag lane 2 disparity-errorflag lane 1 disparity-errorflag lane 0
Table 115. KOUT_FLAG register (address 05h) bit description Bit 3 2 1 0 Symbol DEC_KOUT_LN3 DEC_KOUT_LN2 DEC_KOUT_LN1 DEC_KOUT_LN0 Access R R R R Value Description /K/-symbols found in lane 3 /K/-symbols found in lane 2 /K/-symbols found in lane 1 /K/-symbols found in lane 0
Table 116. K28_LN0_FLAG register (address 06h) bit description Bit 4 3 2 1 0 Symbol K28_7_LN0 K28_5_LN0 K28_4_LN0 K28_3_LN0 K28_0_LN0 Access R R R R R Value Description k28_7 /F/ -symbols found in lane 0 k28_5 /K/ -symbols found in lane 0 k28_4 /Q/ -symbols found in lane 0 k28_3 /A/ -symbols found in lane 0 k28_0 /R/ -symbols found in lane 0
Table 117. K28_LN1_FLAG register (address 07h) bit description Bit 4 3 2 1 0 Symbol K28_7_LN1 K28_5_LN1 K28_4_LN1 K28_3_LN1 K28_0_LN1 Access R R R R R Value Description k28_7 /F/ -symbols found in lane 1 k28_5 /K/ -symbols found in lane 1 k28_4 /Q/ -symbols found in lane 1 k28_3 /A/ -symbols found in lane 1 k28_0 /R/ -symbols found in lane 1
Table 118. K28_LN2_FLAG register (address 08h) bit description Bit 4 3 2 1 0 Symbol K28_7_LN2 K28_5_LN2 K28_4_LN2 K28_3_LN2 K28_0_LN2 Access R R R R R Value Description k28_7 /F/ -symbols found in lane 2 k28_5 /K/ -symbols found in lane 2 k28_4 /Q/ -symbols found in lane 2 k28_3 /A/ -symbols found in lane 2 k28_0 /R/ -symbols found in lane 2
DAC1408D650
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DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 119. K28_LN3_FLAG register (address 09h) bit description Bit 4 3 2 1 0 Symbol K28_7_LN3 K28_5_LN3 K28_4_LN3 K28_3_LN3 K28_0_LN3 Access R R R R R Value Description k28_7 /F/ -symbols found in lane 3 k28_5 /K/ -symbols found in lane 3 k28_4 /Q/ -symbols found in lane 3 k28_3 /A/ -symbols found in lane 3 k28_0 /R/ -symbols found in lane 3
Table 120. KOUT_UNEXPECTED_FLAG register (address 0Ah) bit description Bit 3 2 1 0 Symbol DEC_KOUT_UNEXP_LN3 DEC_KOUT_UNEXP_LN2 DEC_KOUT_UNEXP_LN1 DEC_KOUT_UNEXP_LN0 Access R R R R Value Description Unexpected /K/-symbols found in lane 3 Unexpected /K/-symbols found in lane 2 Unexpected /K/-symbols found in lane 1 Unexpected /K/-symbols found in lane 0
Table 121. LOCK_CNT_MON_LN01 register (address 0Bh) bit description Default settings are shown highlighted. Bit 7 to 4 3 to 0 Symbol LOCK_CNT_MON_LN1[3:0] LOCK_CNT_MON_LN0[3:0] Access R R Value Description lock_state monitor synchronization word alignment lane 1 lock_state monitor synchronization word alignment lane 0
Table 122. LOCK_CNT_MON_LN23 register (address 0Ch) bit description Default settings are shown highlighted. Bit 7 to 4 3 to 0 Symbol LOCK_CNT_MON_LN3[3:0] LOCK_CNT_MON_LN2[3:0] Access R R Value Description lock_state monitor synchronization word alignment lane 3 lock_state monitor synchronization word alignment lane 2
Table 123. CS_STATE_LNX register (address 0Dh) bit description Default settings are shown highlighted. Bit 7 to 6 5 to 4 3 to 2 1 to 0 Symbol CS_STATE_LN3[1:0] CS_STATE_LN2[1:0] CS_STATE_LN1[1:0] CS_STATE_LN0[1:0] Access R R R R Value Description monitor cs_state fsm lane 3 monitor cs_state fsm lane 2 monitor cs_state fsm lane 1 monitor cs_state fsm lane 0
Table 124. RST_BUF_ERR_FLAGS register (address 0Eh) bit description Default settings are shown highlighted. Bit 7 Symbol RST_BUF_ERR_FLAGS Access R/W Value 0 Description reset ila-buf out-of-range_flags
DAC1408D650
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DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 125. INTR_MISC_ENA register (address 0Fh) bit description Default settings are shown highlighted. Bit 7 6 5 4 3 2 1 0 Symbol INTR_ENA_CS_INIT_LN3 INTR_ENA_CS_INIT_LN2 INTR_ENA_CS_INIT_LN1 INTR_ENA_CS_INIT_LN0 INTR_ENA_BUF_ERR_LN3 INTR_ENA_BUF_ERR_LN2 INTR_ENA_BUF_ERR_LN1 INTR_ENA_BUF_ERR_LN0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 0 0 0 0 0 0 0 0 Description intr_misc in case cs_state_ln3 = cs_init intr_misc in case cs_state_ln2 = cs_init intr_misc in case cs_state_ln1 = cs_init intr_misc in case cs_state_ln0 = cs_init intr_misc in case ila_bufcnt_ln3 out-of-range intr_misc in case ila_bufcnt_ln2 out-of-range intr_misc in case ila_bufcnt_ln1 out-of-range intr_misc in case ila_bufcnt_ln0 out-of-range
Table 126. FLAG_CNT_LSB_LN0 register (address 10h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol FLAG_CNT_LN0[7:0] Access R Value Description lsbs of flag_counter lane 0
Table 127. FLAG_CNT_MSB_LN0 register (address 11h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol FLAG_CNT_LN0[15:8] Access R Value Description msbs of flag_counter lane 0
Table 128. FLAG_CNT_LSB_LN1 register (address 12h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol FLAG_CNT_LN1[7:0] Access R Value Description lsbs of flag_counter lane 1
Table 129. FLAG_CNT_MSB_LN1 register (address 13h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol FLAG_CNT_LN1[15:8] Access R Value Description msbs of flag_counter lane 1
Table 130. FLAG_CNT_LSB_LN2 register (address 14h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol FLAG_CNT_LN2[7:0] Access R Value Description lsbs of flag_counter lane 2
Table 131. FLAG_CNT_MSB_LN2 register (address 15h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol FLAG_CNT_LN2[15:8] Access R Value Description msbs of flag_counter lane 2
Table 132. FLAG_CNT_LSB_LN3 register (address 16h) bit description Default settings are shown highlighted. Bit 7 to 0
DAC1408D650
Symbol FLAG_CNT_LN3[7:0]
Access R
Value -
Description lsbs of flag_counter lane 3
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Preliminary data sheet
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 133. FLAG_CNT_MSB_LN3 register (address 17h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol FLAG_CNT_LN3[15:8] Access R Value Description msbs of flag_counter lane 3
Table 134. BER_LEVEL_LSB register (address 18h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol BER_LEVEL[7:0] Access R/W Value 00h Description lsbs level used for simple (dc) ber-measurement
Table 135. BER_LEVEL_MSB register (address 19h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol BER_LEVEL[15:8] Access R/W Value 00h Description msbs level used for simple (dc) ber-measurement
Table 136. INTR_ENA register (address 1Ah) bit description Bit 7 Symbol INTR_ENA_NIT Access R/W 0 1 6 INTR_ENA_DISP R/W 0 1 5 INTR_ENA_KOUT R/W 0 1 4 INTR_ENA_KOUT_UNEXP R/W 0 1 3 INTR_ENA_K28_7 R/W 0 1 2 INTR_ENA_K28_5 R/W 0 1 1 INTR_ENA_K28_3 R/W 0 1 0 INTR_ENA_MISC R/W 0 1 Value Description not-in-table interrupt no action nit-error in ln affects i_ln disparity-error interrupt no action disparity-error in ln affects i_ln k-character interrupt no action detection k-controlcharacter in ln affects i_ln unexpected k-character interrupt no action detection unexpected kchar in ln affects i_ln K28_7 interrupt no action detection k28_7 in ln affects i_ln K28_5 interrupt no action detection k28_5 in ln affects i_ln K28_3 interrupt no action detection k28_3 in ln affects i_ln miscellaneous interrupt no action detection depends on intr_misc_ena (see Table 125)
DAC1408D650
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Preliminary data sheet
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 137. CNTRL_FLAGCNT_LN01 register (address 1Bh) bit description Default settings are shown highlighted. Bit 7 6 to 4 3 2 to 0 Symbol RST_CFC_LN1 SEL_CFC_LN1[2:0] RST_CFC_LN0 SEL_CFC_LN0[2:0] Access R/W R/W R/W R/W Value 0 5h 0 5h Description reset flagcnt lane 1 select cnt-enable flagcnt lane 1 (see Table 142) reset flagcnt lane 0 select cnt-enable flagcnt lane 0 (see Table 142)
Table 138. CNTRL_FLAGCNT_LN23 register (address 1Ch) bit description Default settings are shown highlighted. Bit 7 6 to 4 3 2 to 0 Symbol RST_CFC_LN3 SEL_CFC_LN3[2:0] RST_CFC_LN2 SEL_CFC_LN2[2:0] Access R/W R/W R/W R/W Value 0 5h 0 5h Description reset flagcnt lane 3 select cnt-enable flagcnt lane 3 (see Table 142) reset flagcnt lane 2 select cnt-enable flagcnt lane 2 (see Table 142)
Table 139. MON_FLAGS_RESET register (address 1Dh) bit description Bit 7 6 5 4 3 2 1 0 Symbol RST_NIT_ERR-FLAGS RST_DISP_ERR_FLAGS RST_KOUT_FLAGS RST_K28_LN3_FLAGS RST_K28_LN2_FLAGS RST_K28_LN1_FLAGS RST_K28_LN0_FLAGS Access R/W R/W R/W R/W R/W R/W R/W Value 0 0 0 0 0 0 0 0 Description reset nit-error monitor flags reset disparity monitor flags reset k-symbols monitor flags reset unexpected k-symbols monitor flags reset k28_x monitor flags for lane 3 reset k28_x monitor flags for lane 2 reset k28_x monitor flags for lane 1 reset k28_x monitor flags for lane 0
RST_KOUT_UNEXPECTED_FLAGS R/W
DAC1408D650
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Preliminary data sheet
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DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 140. DBG_CNTRL register (address 1Eh) bit description Bit 7 Symbol BER_MODE Access R/W 0 1 6 INTR_CLEAR R/W 00 01 5 to 3 INTR_MODE[2:0] R/W 000 001 010 011 100 101 110 111 Table 141. PAGE_ADDRESS register (address 1Fh) bit description Bit 2 to 0 Symbol PAGE[2:0] Access R/W Value 0h Description page_address Value Description simple BER-measurement no action simple BER-measurement enabled interrupts clear no action clear interrupts (to '1') interrrupts settings interrupt depends on i_ln0 interrupt depends on i_ln1 interrupt depends on i_ln2 interrupt depends on i_ln3 interrupt depends on i_ln0 or i_ln1 interrupt depends on i_ln2 or i_ln3 interrupt depends on i_ln0 or i_ln1 or i_ln2 or i_ln3 no interrupt
Table 142. Counter source Default settings are shown highlighted. sel_cfc_ln[2:0] 000 001 010 011 100 101 110 111 Source nit_err_ln disp_err_ln kout_ln kout_unexp_ln k28_7_ln (/F/) k28_5_ln (/K/) k28_3_ln (/A/) k28_0_ln (/R/)
DAC1408D650
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Preliminary data sheet
Rev. 02 -- 11 August 2010
76 of 98
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.15.2.11 Page 6 allocation map description
Table 143. Page 6 register allocation map Address 0 1 2 3 4 5 6 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h Register name LN0_CFG_0 LN0_CFG_1 LN0_CFG_2 LN0_CFG_3 LN0_CFG_4 LN0_CFG_5 LN0_CFG_6 LN0_CFG_7 LN0_CFG_8 LN0_CFG_9 LN0_CFG_10 LN0_CFG_11 LN0_CFG_12 LN0_CFG_13 LN1_CFG_0 LN1_CFG_1 LN1_CFG_2 LN1_CFG_3 LN1_CFG_4 LN1_CFG_5 LN1_CFG_6 LN1_CFG_7 LN1_CFG_8 LN1_CFG_9 LN1_CFG_10 LN1_CFG_11 R/W Bit definition b7 R R R R R R R R R R R R R R R R R R R R R R R R R R LN1_CS[1:0] LN1_HD LN1_RES1[7:0] LN1_M[7:0] LN1_N[4:0] LN1_N'[4:0] LN1_S[4:0] LN1_CF[4:0] LN1_SCR LN1_F[7:0] LN1_K[4:0] LN0_CS[1:0] LN0_HD LN0_RES1[7:0] LN0_RES2[7:0] LN0_FCHK[7:0] LN1_DID[7:0] LN1_BID[3:0] LN1_LID[4:0] LN1_L[4:0] LN0_M[7:0] LN0_N[4:0] LN0_N'[4:0] LN0_S[4:0] LN0_CF[4:0] LN0_SCR LN0_F[7:0] LN0_K[4:0] b6 b5 b4 b3 LN0_DID[7:0] LN0_BID[3:0] LN0_LID[4:0] LN0_L[4:0] b2 b1 b0 Default[1] Bin Hex uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu
Preliminary data sheet Rev. 02 -- 11 August 2010 77 of 98
DAC1408D650 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
NXP Semiconductors
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
7 8 9
uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu
10 0Ah 11 0Bh 12 0Ch 13 0Dh 16 10h 17 11h 18 12h 19 13h 20 14h 21 15h 22 16h 23 17h 24 18h 25 19h 26 1Ah 27 1Bh
DAC1408D650
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Table 143. Page 6 register allocation map ...continued Address 28 1Ch 29 1Dh 31 1Fh
[1] Preliminary data sheet Rev. 02 -- 11 August 2010 78 of 98
DAC1408D650 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
NXP Semiconductors
Register name LN1_CFG_12 LN1_CFG_13
R/W Bit definition b7 R R b6 b5 b4 b3 LN1_RES2[7:0] LN1_FCHK[7:0] PAGE[2:0] b2 b1 b0
Default[1] Bin Hex uuuuuuuu 0xuu uuuuuuuu 0xuu 00000000 00h
PAGE_ADDRESS R/W
u = undefined at power-up or after reset.
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
DAC1408D650
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.15.2.12
Page 6 bit definition detailed description Please refer to Table 143 for a register overview and their default values. In the following tables, all the values emphasized in bold are the default values.
Table 144. LN0_CFG_0 register (address 00h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN0_DID[7:0] Access R Value Description lane 0 device ID
Table 145. LN0_CFG_1 register (address 01h) bit description Default settings are shown highlighted. Bit 3 to 0 Symbol LN0_BID[3:0] Access R Value Description lane 0 bank ID
Table 146. LN0_CFG_2 register (address 02h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN0_LID[4:0] Access R Value Description lane 0 lane ID
Table 147. LN0_CFG_3 register (address 03h) bit description Default settings are shown highlighted. Bit 7 4 to 0 Symbol LN0_SCR LN0_L[4:0] Access R R Value Description scrambling on number of lanes
Table 148. LN0_CFG_4 register (address 04h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN0_F[7:0] Access R Value Description number of octets per frame
Table 149. LN0_CFG_5 register (address 05h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN0_K[4:0] Access R Value Description number of frames per multi-frame
Table 150. LN0_CFG_6 register (address 06h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN0_M[7:0] Access R Value Description number of converter per device
Table 151. LN0_CFG_7 register (address 07h) bit description Default settings are shown highlighted. Bit 7 to 6 4 to 0 Symbol LN0_CS[1:0] LN0_N[4:0] Access R R Value Description number of control bits converter resolution
DAC1408D650
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Preliminary data sheet
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DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 152. LN0_CFG_8 register (address 08h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN0_N'[4:0] Access R Value Description number of bits per sample
Table 153. LN0_CFG_9 register (address 09h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN0_S[4:0] Access R Value Description number of samples per converter per frame cycle
Table 154. LN0_CFG_10 register (address 0Ah) bit description Default settings are shown highlighted. Bit 7 4 to 0 Symbol LN0_HD LN0_CF[4:0] Access R R Value Description high density number of control words per frame cycle
Table 155. LN0_CFG_11 register (address 0Bh) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN0_RES1[7:0] Access R Value Description lane 0 reserved field
Table 156. LN0_CFG_12 register (address 0Ch) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN0_RES2[7:0] Access R Value Description lane 0 reserved field
Table 157. LN0_CFG_13 register (address 0Dh) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN0_FCHK[7:0] Access R Value Description lane 0 checksum
Table 158. LN1_CFG_0 register (address 10h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN1_DID[7:0] Access R Value Description lane1 device ID
Table 159. LN1_CFG_1 register (address 11h) bit description Default settings are shown highlighted. Bit 3 to 0 Symbol LN1_BID[3:0] Access R Value Description lane 1 bank ID
Table 160. LN1_CFG_2 register (address 12h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN1_LID[4:0] Access R Value Description lane 1 lane ID
DAC1408D650
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Preliminary data sheet
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 161. LN1_CFG_3 register (address 13h) bit description Default settings are shown highlighted. Bit 7 4 to 0 Symbol LN1_SCR LN1_L[4:0] Access R R Value Description scrambling on number of lanes
Table 162. LN1_CFG_4 register (address 14h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN1_F[7:0] Access R Value Description number of octets per frame
Table 163. LN1_CFG_5 register (address 15h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN1_K[4:0] Access R Value Description number of frames per multiframe
Table 164. LN1_CFG_6 register (address 16h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN1_M[7:0] Access R Value Description number of converter per device
Table 165. LN1_CFG_7 register (address 17h) bit description Default settings are shown highlighted. Bit 7 to 6 4 to 0 Symbol LN1_CS[1:0] LN1_N[4:0] Access R R Value Description number of control bits converter resolution
Table 166. LN1_CFG_8 register (address 18h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN1_N'[4:0] Access R Value Description number of bits per sample
Table 167. LN1_CFG_9 register (address 19h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN1_S[4:0] Access R Value Description number of samples per converter per frame cycle
Table 168. LN1_CFG_10 register (address 1Ah) bit description Default settings are shown highlighted. Bit 7 to 6 4 to 0 Symbol LN1_HD LN1_CF[4:0] Access R R Value Description high density number of control words per frame cycle
Table 169. LN1_CFG_11 register (address 1Bh) bit description Default settings are shown highlighted. Bit 7 to 0
DAC1408D650
Symbol LN1_RES1[7:0]
Access R
Value -
Description lane 1 reserved field
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All information provided in this document is subject to legal disclaimers.
Preliminary data sheet
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NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 170. LN1_CFG_12 register (address 1Ch) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN1_RES2[7:0] Access R Value Description lane 1 reserved field
Table 171. LN1_CFG_13 register (address 1Dh) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN1_FCHK[7:0] Access R Value Description lane 1 checksum
Table 172. PAGE_ADDRESS register (address 1Fh) bit description Default settings are shown highlighted. Bit 2 to 0 Symbol PAGE[2:0] Access R Value 0h Description page_address
DAC1408D650
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Preliminary data sheet
Rev. 02 -- 11 August 2010
82 of 98
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.15.2.13 Page 7 allocation map description
Table 173. Page 7 register allocation map Address 0 1 2 3 4 5 6 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h Register name LN2_CFG_0 LN2_CFG_1 LN2_CFG_2 LN2_CFG_3 LN2_CFG_4 LN2_CFG_5 LN2_CFG_6 LN2_CFG_7 LN2_CFG_8 LN2_CFG_9 LN2_CFG_10 LN2_CFG_11 LN2_CFG_12 LN2_CFG_13 LN3_CFG_0 LN3_CFG_1 LN3_CFG_2 LN3_CFG_3 LN3_CFG_4 LN3_CFG_5 LN3_CFG_6 LN3_CFG_7 LN3_CFG_8 LN3_CFG_9 LN3_CFG_10 LN3_CFG_11 R/W Bit definition b7 R R R R R R R R R R R R R R R R R R R R R R R R R R LN3_CS[1:0] LN3_HD LN3_RES1[7:0] LN3_M[7:0] LN3_N[4:0] LN3_N'[4:0] LN3_S[4:0] LN3_CF[4:0] LN3_SCR LN3_F[7:0] LN3_K[4:0] LN2_CS[1:0] LN2_HD LN2_RES1[7:0] LN2_RES2[7:0] LN2_FCHK[7:0] LN3_DID[7:0] LN3_BID[3:0] LN3_LID[4:0] LN3_L[4:0] LN2_M[7:0] LN2_N[4:0] LN2_N'[4:0] LN2_S[4:0] LN2_CF[4:0] LN2_SCR LN2_F[7:0] LN2_K[4:0] b6 b5 b4 b3 LN2_DID[7:0] LN2_BID[3:0] LN2_LID[4:0] LN2_L[4:0] b2 b1 b0 Default[1] Bin Hex uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu
Preliminary data sheet Rev. 02 -- 11 August 2010 83 of 98
DAC1408D650 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
NXP Semiconductors
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
7 8 9
uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu uuuuuuuu 0xuu
10 0Ah 11 0Bh 12 0Ch 13 0Dh 16 10h 17 11h 18 12h 19 13h 20 14h 21 15h 22 16h 23 17h 24 18h 25 19h 26 1Ah 27 1Bh
DAC1408D650
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 173. Page 7 register allocation map ...continued Address 28 1Ch 29 1Dh 31 1Fh
[1] Preliminary data sheet Rev. 02 -- 11 August 2010 84 of 98
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NXP Semiconductors
Register name LN3_CFG_12 LN3_CFG_13
R/W Bit definition b7 R R b6 b5 b4 b3 LN3_RES2[7:0] LN3_FCHK[7:0] PAGE[2:0] b2 b1 b0
Default[1] Bin Hex uuuuuuuu 0xuu uuuuuuuu 0xuu 00000000 00h
PAGE_ADDRESS R/W
u = undefined at power-up or after reset.
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
DAC1408D650
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
10.15.2.14
Page 7 bit definition detailed description Please refer to Table 173 for a register overview and their default values. In the following tables, all the values emphasized in bold are the default values.
Table 174. LN2_CFG_0 register (address 00h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN2_DID[7:0] Access R Value Description lane2 device ID
Table 175. LN2_CFG_1 register (address 01h) bit description Default settings are shown highlighted. Bit 3 to 0 Symbol LN2_BID[3:0] Access R Value Description lane 2 bank ID
Table 176. LN2_CFG_2 register (address 02h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN2_LID[4:0] Access R Value Description lane 2 lane ID
Table 177. LN2_CFG_3 register (address 03h) bit description Default settings are shown highlighted. Bit 7 4 to 0 Symbol LN2_SCR LN2_L[4:0] Access R R Value Description scrambling on number of lanes
Table 178. LN2_CFG_4 register (address 04h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN2_F[7:0] Access R Value Description number of octets per frame
Table 179. LN2_CFG_5 register (address 05h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN2_K[4:0] Access R Value Description number of frames per multiframe
Table 180. LN2_CFG_6 register (address 06h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN2_M[7:0] Access R Value Description number of converter per device
Table 181. LN2_CFG_7 register (address 07h) bit description Default settings are shown highlighted. Bit 7 to 6 4 to 0 Symbol LN2_CS[1:0] LN2_N[4:0] Access R R Value Description number of control bits converter resolution
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Table 182. LN2_CFG_8 register (address 08h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN2_N'[4:0] Access R Value Description number of bits per sample
Table 183. LN2_CFG_9 register (address 09h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN2_S[4:0] Access R Value Description number of samples per converter per frame cycle
Table 184. LN2_CFG_10 register (address 0Ah) bit description Default settings are shown highlighted. Bit 7 4 to 0 Symbol LN2_HD LN2_CF[4:0] Access R R Value Description high density number of control words per frame cycle
Table 185. LN2_CFG_11 register (address 0Bh) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN2_RES1[7:0] Access R Value Description lane 2 reserved field
Table 186. LN2_CFG_12 register (address 0Ch) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN2_RES2[7:0] Access R Value Description lane 2 reserved field
Table 187. LN2_CFG_13 register (address 0Dh) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN2_FCHK[7:0] Access R Value Description lane 2 checksum
Table 188. LN3_CFG_0 register (address 10h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN3_DID[7:0] Access R Value Description lane 3 device ID
Table 189. LN3_CFG_1 register (address 11h) bit description Default settings are shown highlighted. Bit 3 to 0 Symbol LN3_BID[3:0] Access R Value Description lane 3 bank ID
Table 190. LN3_CFG_2 register (address 12h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN3_LID[4:0] Access R Value Description lane 3 lane ID
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Table 191. LN3_CFG_3 register (address 13h) bit description Default settings are shown highlighted. Bit 7 4 to 0 Symbol LN3_SCR LN3_L[4:0] Access R R Value Description scrambling on number of lanes
Table 192. LN3_CFG_4 register (address 14h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN3_F[7:0] Access R Value Description number of octets per frame
Table 193. LN3_CFG_5 register (address 15h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN3_K[4:0] Access R Value Description number of frames per multiframe
Table 194. LN3_CFG_6 register (address 16h) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN3_M[7:0] Access R Value Description number of converter per device
Table 195. LN3_CFG_7 register (address 17h) bit description Default settings are shown highlighted. Bit 7 to 6 4 to 0 Symbol LN3_CS[1:0] LN3_N[4:0] Access R R Value Description number of control bits converter resolution
Table 196. LN3_CFG_8 register (address 18h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN3_N'[4:0] Access R Value Description number of bits per sample
Table 197. LN3_CFG_9 register (address 19h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN3_S[4:0] Access R Value Description number of samples per converter per frame cycle
Table 198. LN3_CFG_10 register (address 1Ah) bit description Default settings are shown highlighted. Bit 7 4 to 0 Symbol LN3_HD LN3_CF[4:0] Access R R Value Description high density number of control words per frame cycle
Table 199. LN3_CFG_11 register (address 1Bh) bit description Default settings are shown highlighted. Bit 7 to 0
DAC1408D650
Symbol LN3_RES1[7:0]
Access R
Value -
Description lane 3 reserved field
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DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 200. LN3_CFG_12 register (address 1Ch) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN3_RES2[7:0] Access R Value Description lane 3 reserved field
Table 201. LN3_CFG_13 register (address 1Dh) bit description Default settings are shown highlighted. Bit 7 to 0 Symbol LN3_FCHK[7:0] Access R Value Description lane 3 checksum
Table 202. PAGE_ADDRESS register (address 1Fh) bit description Default settings are shown highlighted. Bit 2 to 0 Symbol PAGE[2:0] Access R/W Value 0h Description page_address
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DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
11. Package outline
HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm
SOT804-3
D
B
A
terminal 1 index area
E
A
A1 c detail X
e1 1/2 e L 17 16 e b 32 33 v w CAB C y1 C C y
e Eh 1/2 e e2
1 terminal 1 index area 64 Dh 49
48 X
0 Dimensions Unit mm A A1 b c 0.2 D(1) 9.1 9.0 8.9 Dh 7.25 7.10 6.95 E(1) 9.1 9.0 8.9 Eh 7.25 7.10 6.95 e 0.5
2.5 scale e1 7.5 e2 7.5
5 mm
L 0.5 0.4 0.3
v 0.1
w
y
y1 0.1
max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18
0.05 0.05
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT804-3 References IEC --JEDEC --JEITA --European projection
sot804-3_po
Issue date 09-02-24 10-08-06
Fig 27. Package outline SOT804-3 (HVQFN64)
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12. Abbreviations
Table 203. Abbreviations Acronym AQM BW BWA CDMA CML CMOS DAC EDGE FIR GSM IF IMD3 LMDS LTE LVDS NCO NMOS PLL SERDES SFDR SPI TD-SCDMA WCDMA WiMax WLL Description Analog Quadrature Modulator BandWidth Broadband Wireless Access Code Division Multiple Access Current Mode Logic Complementary Metal Oxide Semiconductor Digital-to-Analog Converter Enhanced Data rates for GSM Evolution Finite Impulse Response Global System for Mobile communications Intermediate Frequency third order InterMoDulation Product Local Multipoint Distribution Service Long Term Evolution Low-voltage Differential Signaling Numerically Controlled Oscillator Negative Metal-Oxide Semiconductor Phase-Locked Loop Serializer/Deserializer Spurious Free Dynamic Range Serial Peripheral Interface Time Division-Synchronous Code Division Multiple Access Wideband Code Division Multiple Access Worldwide interoperability for Microwave Access Wireless Local Loop
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DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
13. Revision history
Table 204. Revision history Document ID DAC1408D650 v.2 Modifications: DAC1408D650_1 Release date 20100811 Data sheet status Preliminary data sheet Change notice Supersedes DAC1408D650_1
* *
Template upgraded to Rev 2.12.0 including revised legal information. Text and drawings updated throughout entire data sheet. Objective data sheet -
20090526
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14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
(c) NXP B.V. 2010. All rights reserved.
14.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
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DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
16. Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .6 Thermal characteristics . . . . . . . . . . . . . . . . . . .6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .7 Digital Layer Processing Latency . . . . . . . . . . .12 SYNC_OUT timing . . . . . . . . . . . . . . . . . . . . . .14 Read or Write mode access description . . . . .23 Number of bytes to be transferred . . . . . . . . . .23 SPI timing characteristics . . . . . . . . . . . . . . . .24 Interpolation filter coefficients . . . . . . . . . . . . .26 Inversion filter coefficients . . . . . . . . . . . . . . . .28 DAC transfer function . . . . . . . . . . . . . . . . . . .28 IO(fs) coarse adjustment . . . . . . . . . . . . . . . . . .30 IO(fs) fine adjustment . . . . . . . . . . . . . . . . . . . .30 Digital offset adjustment . . . . . . . . . . . . . . . . .31 Auxiliary DAC transfer function . . . . . . . . . . . .32 Page 0 register allocation map . . . . . . . . . . . .38 COMMON register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .40 TXCFG register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .40 PLLCFG register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .41 FREQNCO_LSB register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .41 FREQNCO_LISB register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .41 FREQNCO_UISB register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .41 FREQNCO_MSB register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .42 PHINCO_LSB register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .42 PHINCO_MSB register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .42 DAC_A_CFG_1 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .42 DAC_A_CFG_2 register (address 0Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .42 DAC_A_CFG_3 register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .42 DAC_B_CFG_1 register (address 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .43 DAC_B_CFG_2 register (address 0Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .43 DAC_B_CFG_3 register (address 0Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .43 Table 34. DAC_CFG register (address 0Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 35. DAC_CURRENT_0 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 36. DAC_CURRENT_1 register (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 37. DAC_CURRENT_2 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 38. DAC_CURRENT_3 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 39. DAC_SEL_PH_FINE register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 40. PHASECORR_CNTRL0 register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 41. PHASECORR_CNTRL1 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 42. DAC_A_AUX_MSB register (address 1Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 43. DAC_A_AUX_LSB register (address 1Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 44. DAC_B_AUX_MSB register (address 1Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 45. DAC_B_AUX_LSB register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 46. DAC_B_AUX_LSB register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 47. Bias current control table . . . . . . . . . . . . . . . . . 45 Table 48. Page 1 register allocation map . . . . . . . . . . . . 46 Table 49. MDS_MAIN register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 50. MDS_WIN_PERIOD_A register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 51. MDS_WIN_PERIOD_B register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 52. MDS_MISCCNTRL0 register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 53. MDS_MAN_ADJUSTDLY register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 54. MDS_AUTO_CYCLES register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 55. MDS_MISCCNTRL1 register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 56. MDS_ADJDELAY register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 57. MDS_STATUS0 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 58. MDS_STATUS1 register (address 0Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50
continued >>
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Preliminary data sheet
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DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
Table 87. ILA_CNTRL register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 88. FORCE_ALIGN register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 89. MAN_ALIGN_LN_0_1 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 90. MAN_ALIGN_LN_2_3 register (address 0Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 91. FA_ERR_HANDLING register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 92. SYNCOUT_MODE register (address 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 93. LANE_POLARITY register (address 0Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 94. LANE_SELECT register (address 0Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 95. SOFT_RESET_SCRAMBLER register (address 10h) bit description . . . . . . . . . . . . . . 64 Table 96. INIT_SCR_S15T8_LN0 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 97. INIT_SCR_S7T1_LN0 (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 98. INIT_SCR_S15T8_LN1 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 99. INIT_SCR_S7T1_LN1 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 100. INIT_SCR_S15T8_LN2 register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 101. INIT_SCR_S7T1_LN2 register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 102. INIT_SCR_S15T8_LN3 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 103. INIT_SCR_S7T1_LN3 register (address 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 104. INIT_ILA_BUFPTR_LN01 register (address 19h) bit description . . . . . . . . . . . . . . 65 Table 105. INIT_ILA_BUFPTR_LN23 register (address 1Ah) bit description . . . . . . . . . . . . . 65 Table 106. ERROR_HANDLING register (address 1Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 107. REINIT_CNTRL register (address 1Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 108. PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 109. Page 5 register allocation map . . . . . . . . . . . . 68 Table 110. ILA_MON_1_0 register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 111. ILA_MON_3_2 register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 112. ILA_BUF_ERR register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 59. PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 60. Page 2 register allocation map . . . . . . . . . . . .51 Table 61. MAINCONTROL register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 62. JCLK_CNTRL register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 63. RST_EXT_FCLK register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 64. RST_EXT_DCLK register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 65. DCSMU_PREDIVCNT register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 66. PLL_CHARGETIME register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 67. PLL_RUN_IN_TIME register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 68. CA_RUN_IN_TIME register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 69. SET_VCM_VOLTAGE register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 70. SET_SYNC register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 71. TYPE_ID register (address 1Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 Table 72. DAC_VERSION register (address 1Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 Table 73. DIG_VERSION register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 Table 74. JRX_ANA_VERSION register (address 1Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 Table 75. PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 Table 76. Lane common-mode voltage adjustment . . . . .55 Table 77. SYNC common-mode voltage adjustment . . . .55 Table 78. SYNC swing voltage adjustment . . . . . . . . . . .55 Table 79. Page 4 register allocation map . . . . . . . . . . . .56 Table 80. SR_DLP_0 register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .58 Table 81. SR_DLP_1 register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .58 Table 82. FORCE_LOCK register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .58 Table 83. MAN_LOCK_LN_1_0 register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .59 Table 84. MAN_LOCK_2_0 register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .59 Table 85. CA_CNTRL register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .59 Table 86. SCR-CNTRL register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .60
continued >>
DAC1408D650
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
95 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 139. MON_FLAGS_RESET register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 140. DBG_CNTRL register (address 1Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 141. PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 142. Counter source . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 143. Page 6 register allocation map . . . . . . . . . . . . 77 Table 144. LN0_CFG_0 register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 145. LN0_CFG_1 register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 146. LN0_CFG_2 register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 147. LN0_CFG_3 register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 148. LN0_CFG_4 register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 149. LN0_CFG_5 register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 150. LN0_CFG_6 register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 151. LN0_CFG_7 register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 152. LN0_CFG_8 register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 153. LN0_CFG_9 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 154. LN0_CFG_10 register (address 0Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 155. LN0_CFG_11 register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 156. LN0_CFG_12 register (address 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 157. LN0_CFG_13 register (address 0Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 158. LN1_CFG_0 register (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 159. LN1_CFG_1 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 160. LN1_CFG_2 register (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 161. LN1_CFG_3 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 162. LN1_CFG_4 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 163. LN1_CFG_5 register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 164. LN1_CFG_6 register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 113. CA_MON register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .70 Table 114. DEC_FLAGS register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 115. KOUT_FLAG register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 116. K28_LN0_FLAG register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 117. K28_LN1_FLAG register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 118. K28_LN2_FLAG register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 119. K28_LN3_FLAG register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .72 Table 120. KOUT_UNEXPECTED_FLAG register (address 0Ah) bit description . . . . . . . . . . . . . .72 Table 121. LOCK_CNT_MON_LN01 register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .72 Table 122. LOCK_CNT_MON_LN23 register (address 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .72 Table 123. CS_STATE_LNX register (address 0Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .72 Table 124. RST_BUF_ERR_FLAGS register (address 0Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .72 Table 125. INTR_MISC_ENA register (address 0Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 126. FLAG_CNT_LSB_LN0 register (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 127. FLAG_CNT_MSB_LN0 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 128. FLAG_CNT_LSB_LN1 register (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 129. FLAG_CNT_MSB_LN1 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 130. FLAG_CNT_LSB_LN2 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 131. FLAG_CNT_MSB_LN2 register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 132. FLAG_CNT_LSB_LN3 register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 133. FLAG_CNT_MSB_LN3 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .74 Table 134. BER_LEVEL_LSB register (address 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .74 Table 135. BER_LEVEL_MSB register (address 19h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .74 Table 136. INTR_ENA register (address 1Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .74 Table 137. CNTRL_FLAGCNT_LN01 register (address 1Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .75 Table 138. CNTRL_FLAGCNT_LN23 register (address 1Ch)
continued >>
DAC1408D650
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
96 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 195. LN3_CFG_7 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 196. LN3_CFG_8 register (address 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 197. LN3_CFG_9 register (address 19h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 198. LN3_CFG_10 register (address 1Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 199. LN3_CFG_11 register (address 1Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 200. LN3_CFG_12 register (address 1Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 201. LN3_CFG_13 register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 202. PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 203. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 204. Revision history . . . . . . . . . . . . . . . . . . . . . . . 91
Table 165. LN1_CFG_7 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 166. LN1_CFG_8 register (address 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 167. LN1_CFG_9 register (address 19h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 168. LN1_CFG_10 register (address 1Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 169. LN1_CFG_11 register (address 1Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 170. LN1_CFG_12 register (address 1Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .82 Table 171. LN1_CFG_13 register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .82 Table 172. PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .82 Table 173. Page 7 register allocation map . . . . . . . . . . . .83 Table 174. LN2_CFG_0 register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 Table 175. LN2_CFG_1 register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 Table 176. LN2_CFG_2 register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 Table 177. LN2_CFG_3 register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 Table 178. LN2_CFG_4 register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 Table 179. LN2_CFG_5 register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 Table 180. LN2_CFG_6 register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 Table 181. LN2_CFG_7 register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 Table 182. LN2_CFG_8 register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 Table 183. LN2_CFG_9 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 Table 184. LN2_CFG_10 register (address 0Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 Table 185. LN2_CFG_11 register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 Table 186. LN2_CFG_12 register (address 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 Table 187. LN2_CFG_13 register (address 0Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 Table 188. LN3_CFG_0 register (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 Table 189. LN3_CFG_1 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 Table 190. LN3_CFG_2 register (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 Table 191. LN3_CFG_3 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .87 Table 192. LN3_CFG_4 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .87 Table 193. LN3_CFG_5 register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .87 Table 194. LN3_CFG_6 register (address 16h)
DAC1408D650
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 02 -- 11 August 2010
97 of 98
NXP Semiconductors
DAC1408D650
DAC1408D; up to 650 Msps; 2x, 4x or 8x interpolating with JESD204A
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Thermal characteristics . . . . . . . . . . . . . . . . . . 6 9 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 Application information. . . . . . . . . . . . . . . . . . 11 10.1 General description . . . . . . . . . . . . . . . . . . . . 11 10.2 JESD204A receiver . . . . . . . . . . . . . . . . . . . . 12 10.2.1 Lane input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10.2.2 Sync and word align . . . . . . . . . . . . . . . . . . . . 13 10.2.3 Comma detection and word align . . . . . . . . . . 14 10.2.4 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10.2.5 Interlane alignment . . . . . . . . . . . . . . . . . . . . . 15 10.2.5.1 Single device operation . . . . . . . . . . . . . . . . . 15 10.2.5.2 Multi-device operation . . . . . . . . . . . . . . . . . . 16 10.2.5.3 Master/slave mode . . . . . . . . . . . . . . . . . . . . . 17 10.2.5.4 All slave mode . . . . . . . . . . . . . . . . . . . . . . . . 20 10.2.6 Frame assembly . . . . . . . . . . . . . . . . . . . . . . . 21 10.3 Serial Peripheral Interface (SPI) . . . . . . . . . . . 23 10.3.1 Protocol description . . . . . . . . . . . . . . . . . . . . 23 10.3.2 SPI timing description . . . . . . . . . . . . . . . . . . . 24 10.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.5 FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.6 Quadrature modulator and Numerically Controlled Oscillator (NCO) . . . . . . . . . . . . . . 27 10.6.1 NCO in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.6.2 Low-power NCO . . . . . . . . . . . . . . . . . . . . . . . 27 10.6.3 Minus_3dB . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.7 x / (sin x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.8 DAC transfer function . . . . . . . . . . . . . . . . . . . 28 10.9 Full scale current . . . . . . . . . . . . . . . . . . . . . . 29 10.9.1 Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.9.1.1 External regulation . . . . . . . . . . . . . . . . . . . . . 29 10.9.2 Full scale current adjustment . . . . . . . . . . . . . 29 10.10 Digital offset adjustment . . . . . . . . . . . . . . . . . 30 10.11 Analog output . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.12 Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 32 10.13 Output configuration . . . . . . . . . . . . . . . . . . . . 33 10.13.1 Basic output configuration . . . . . . . . . . . . . . . 33 DC interface to an Analog Quadrature Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 10.13.3 AC interface to an Analog Quadrature Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 10.13.4 Phase correction . . . . . . . . . . . . . . . . . . . . . . 10.14 Power and grounding. . . . . . . . . . . . . . . . . . . 10.15 Configuration interface. . . . . . . . . . . . . . . . . . 10.15.1 Register description . . . . . . . . . . . . . . . . . . . . 10.15.2 Detailed descriptions of registers . . . . . . . . . . 10.15.2.1 Page 0 allocation map description . . . . . . . . . 10.15.2.2 Page 0 bit definition detailed description . . . . 10.15.2.3 Page 1 allocation map description . . . . . . . . . 10.15.2.4 Page 1 bit definition detailed description . . . . 10.15.2.5 Page 2 allocation map description . . . . . . . . . 10.15.2.6 Page 2 bit definition detailed description . . . . 10.15.2.7 Page 4 allocation map description . . . . . . . . . 10.15.2.8 Page 4 bit definition detailed description . . . . 10.15.2.9 Page 5 allocation map description . . . . . . . . . 10.15.2.10 Page 5 bit definition detailed description . . . 10.15.2.11 Page 6 allocation map description . . . . . . . . 10.15.2.12 Page 6 bit definition detailed description . . . 10.15.2.13 Page 7 allocation map description . . . . . . . . 10.15.2.14 Page 7 bit definition detailed description . . . 11 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information . . . . . . . . . . . . . . . . . . . . . . 14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information . . . . . . . . . . . . . . . . . . . . 16 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.13.2 34 36 37 37 37 37 37 38 40 46 47 51 52 56 58 68 70 77 79 83 85 89 90 91 92 92 92 92 93 93 94 98
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 August 2010 Document identifier: DAC1408D650

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